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? 2005 - 2015 microchip technology inc. ds00002020a-page 1 product features ? 3.3 volt operation (5v tolerant) ? programmable wakeup event interface (io_pme# pin) ? smi support (io_smi# pin) ? gpios (16) ? programmable internal pull-up resistors ? two irq input pins ? xnor chain ? pc99a and acpi 1.0 compliant ? 64-pin stqfp rohs compliant package ? intelligent auto power management ? one full function serial port - high speed 16c550a compatible uarts with send/receive 16-byte fifos - supports 230k and 460k baud - programmable baud rate generator - modem control circuitry ? infrared communications controller - three ir ports - multi-protocol serial communications con- trollers - two irda v1.2 (4mbps ), hpsir, askir, con- sumer ir support - one consumer ir port with support for nec ppm and rc5 with pme wake-up option - multiple base i/o address options, 15 irq options and 3 dma options ? lpc bus host interface - supports lpc bus frequencies of 19.2mhz to 33mhz - multiplexed command, address and data bus - 8-bit i/o transfers - 8-bit dma transfers - 16-bit address qualification - serial irq interface compatible with serial- ized irq support for pci systems - pci nclkrun support - power management event (io_pme#) inter- face pin ? lpc portswitch interface - secondary switchable lpc interface (3.3v only) - trusted cycles blocked - buffered 14 mhz output - switched pci clock output description the microchip SIO1007 is a 3.3v pc 99 and acpi 1.0 compliant super i/o controller. the SIO1007 imple- ments the lpc interface with the lpc portswitch interface. t he lpc portswitch interface is a hot- switchable external dock ing lpc interface with trusted cycle block. the SIO1007 also features a full 16-bit internally decoded address bus, a serial irq interface with pci nclkrun support, relocatable con- figuration ports and three dma channel options. the part also includes 16 gpio pins. the SIO1007 incorporates one 8-pin 16c550a com- patible uart. in addition, the SIO1007 provides a sec- ond uart to support a serial infrared interface that complies with irda v1.2 (f ast ir), hpsir, and askir formats, as well as consumer ir. there is a second ir port, which supports nec ppm and rc5, as well as consumer ir protocols. the SIO1007 incorporates sophisticated power control circuitry (pcc). the pcc supports multiple low power down modes. the SIO1007 also features software configurable logic (scl) for ease of use. scl allows programmable system configur ation of key functions such as the uarts. the SIO1007 supports the isa plug-and-play standard register set (version 1.0a ) and provides the recom- mended functionality to support windows ?9x, 2k, me, xp and pc99. the i/o address, dma channel and hardware irq of each device in the SIO1007 may be reprogrammed through the inte rnal configuration regis- ters. there are 192 i/o address location options, a serialized irq interface, and three dma channels. SIO1007 lpc super i/o lpc irda hot docking chip with uart
SIO1007 ds00002020a-page 2 ? 2005 - 2015 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the versi on number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operati onal differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/doc umentation issues become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exis ts for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2005 - 2015 microchip technology inc. ds00002020a-page 3 SIO1007 table of contents 1.0 block diagram ............................................................................................................. .................................................................... 4 2.0 pin layout ................................................................................................................ ....................................................................... 5 3.0 pin configuration ......................................................................................................... ................................................................... 6 4.0 signal description ........................................................................................................ ................................................................... 7 5.0 power functionality ....................................................................................................... ................................................................ 12 6.0 super i/o registers ....................................................................................................... ............................................................... 14 7.0 lpc interface ............................................................................................................. ................................................................... 15 8.0 lpc portswitch ............................................................................................................ ................................................................. 18 9.0 serial port (uart) ........................................................................................................ ................................................................ 21 10.0 infrared interface ....................................................................................................... .................................................................. 34 11.0 power management ......................................................................................................... ........................................................... 40 12.0 serial irq ............................................................................................................... .................................................................... 41 13.0 pci clkrun support ....................................................................................................... .......................................................... 45 14.0 general purpose i/o ...................................................................................................... ............................................................. 47 15.0 system management interrupt (smi) ........................................................................................ .................................................. 51 16.0 pme support .............................................................................................................. ................................................................. 52 17.0 runtime registers ........................................................................................................ .............................................................. 53 18.0 configuration ............................................................................................................ ................................................................... 57 19.0 operational description .................................................................................................. ............................................................ 87 20.0 timing diagrams .......................................................................................................... ............................................................... 90 21.0 xnor-chain test mode ..................................................................................................... ...................................................... 100 22.0 package outline .......................................................................................................... .............................................................. 103 appendix a: data sheet revision history ....................................................................................... .................................................. 104 the microchip web site ........................................................................................................ ............................................................ 105 customer change notification service .......................................................................................... ................................................... 105 customer support .............................................................................................................. ............................................................... 105 product identification system ................................................................................................. .......................................................... 106
SIO1007 ds00002020a-page 4 ? 2005 - 2015 microchip technology inc. 1.0 block diagram 1.1 reference documents ? circc 2.x block product architecture specific ation revision 0.7, dated august 26, 2004 ? ircc 2.x block data sheet/product architecture specification (contact microchip, unpublished) figure 1-1: SIO1007 block diagram txd1, nrts1, ndtr1 nio_pme irtx2, irmode* irrx2, irrx3*, host lpc bus interface clock gen smi pme wdt (uart1) 16c550 compatible serial port 1 ncts1, rxd1, ndsr1, ndcd1, nri1 configuration registers general purpose i/o gp30-gp37 gp10-gp11 gp15*,gp16* gp17 gp12*, gp13*, gp14*, control, address, data acpi block nio_smi* 16c550 compatible 2 pin infrared interface serial port irqin1*, irqin2*, sio_14m lad[3:0] lframe# ldrq0# ldrq1# pci_reset# lpcpd# nclkrun pci_clk ser_irq nio_pme lpc_clk_33 dsio_14m dlad[3:0] dlframe# dldrq1# ndclkrun dlpc_clk_33 dser_irq dock lpc bus interface docking lpc switche s buffers and control sio_14m denotes multifunction pins * cirtx cirrx circc2 block clki32
? 2005 - 2015 microchip technology inc. ds00002020a-page 5 SIO1007 2.0 pin layout figure 2-1: SIO1007 64 pin stqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 dlad[1] lad[1] dlad[2] lad[2] vcc dlad[3] lad[3] vss dlpc_clk_33 lpc_clk_33 ndldrq1 nldrq1 ndlframe nlframe ndclkrun nclkrun vtr nio_pme gp36 vss gp35 gp34 vcc gp33 gp32 gp31 gp30 vss gp17 gp16/cirtx gp15/cirrx gp14 / irqin2 vcc dser_irq ser_irq vss pci_clk npci_reset sio_14m nldrq0 nlpcpd dsio_14m gp10 gp11 vss gp12 / nio_smi vcc gp13 / irqin1 / clki32 lad[0] dlad[0] vss gp37 vcc ndcd1 nri1 ndtr1/ sysopt1 ncts1 nrts1/sysopt0 ndsr1 txd1 rxd1 irmode/irrx3 irrx2 irtx2 64 pin stqfp
SIO1007 ds00002020a-page 6 ? 2005 - 2015 microchip technology inc. 3.0 pin configuration table 3-1: pin configuration pin# name pin# name pin# name pin# name 1 dlad[1] 17 vcc 33 gp14 / irqin2 49 irtx2 2 lad[1] 18 dser_irq 34 gp15/cirrx 50 irrx2 3 dlad[2] 19 ser_irq 35 gp16/cirtx 51 irmode/irrx3 4 lad[2] 20 vss 36 gp17 52 rxd1 5 vcc 21 pci_clk 37 vss 53 txd1 6 dlad[3] 22 npci_reset 38 gp30 54 ndsr1 7 lad[3] 23 sio_14m 39 gp31 55 nrts1/sysopt0 8 vss 24 nldrq0 40 gp32 56 ncts1 9 dlpc_clk_33 25 nlpcpd 41 gp33 57 ndtr1/ sysopt1 10 lpc_clk_33 26 dsio_14m 42 vcc 58 nri1 11 ndldrq1 27 gp10 43 gp34 59 ndcd1 12 nldrq1 28 gp11 44 gp35 60 vcc 13 ndlframe 29 vss 45 vss 61 gp37 14 nlframe 30 gp12 / nio_smi 46 gp36 62 vss 15 ndclkrun 31 vcc 47 nio_pme 63 dlad[0] 16 nclkrun 32 gp13 /irqin1 / clki32 48 vtr 64 lad[0]
? 2005 - 2015 microchip technology inc. ds00002020a-page 7 SIO1007 4.0 signal description 4.1 pin functions table 4-1: pin functions stqfp pin # name description buffer name input buffer power well output buffer power well notes power and ground pins (18) 5, 17, 31, 42, 60 vcc +3.3 volt supply voltage 48 vtr +3.3 volt standby supply voltage 23 vbat battery voltage 8, 20, 29, 37, 45, 62 vss ground clock (1) 23 sio_14m 14.318mhz clock input i vcc n/a processor/host lpc interface (11) 19 ser_irq serial irq pin used with the pci_clk pin to transfer interrupts from this device to the host. pci_io vcc vcc 4-3 7,4,2, 64 lad[3:0] active high lpc i/o used for multiplexed command, address and data bus. pci_io vcc vcc 4-3 14 nlframe active low input indicates start of new cycle and termination of broken cycle. pci_i vcc n/a 4-3 24 nldrq0 active low output used for encoded dma/bus master request for the lpc interface. pci_o vcc vcc 4-3 12 nldrq1 active low signal between this device and the lpc host used for encoded dma/bus master request for docking lpc super i/o to the lpc host. pci_o vcc vcc 4-3 22 npci_reset active low input used as lpc interface reset. pci_i vcc n/a 25 nlpcpd active low input power down signal indicates that this device should prepare for power to be shut-off on the lpc interface. pci_i vcc n/a 4-1 4-3 21 pci_clk pci clock input. pci_iclk vcc n/a 10 lpc_clk_33 pci clock input from clock source dedicated to docking interface. vcc vcc 4-3 16 nclkrun this signal is used to indicate the pci clock status and to request that a stopped clock be started. pci_od vcc vcc 4-3 dock interface(11) 18 dser_irq serial irq pin between this device and the docking lpc sio used with the dlpc_clk_33 pin to transfer interrupts between this device and the lpc host. vcc vcc 4-3
SIO1007 ds00002020a-page 8 ? 2005 - 2015 microchip technology inc. 6,3,1, 63 dlad[3:0] active high lpc signals used for multiplexed command, address and data bus between this device and the docking lpc sio. vcc vcc 4-3 13 ndlframe active low signal indicates start of new cycle and termination of broken cycle to the docking lpc sio. vcc vcc 4-3 11 ndldrq1 active low signal between this device and the lpc host used for encoded dma/bus master request for docking lpc super i/o to the lpc host. vcc vcc 4-3 9 dlpc_clk_33 dedicated pci clock switch output between this device and the docking lpc sio. vcc 4-3 15 ndclkrun this signal between this device and the docking lpc sio is used to indicate the pci clock status and to request that a stopped clock be started. vcc vcc 4-3 26 dsio_14m buffered 14 mhz clock output between this device and the docking lpc sio. o24 vcc serial port interface (8) 59 ndcd1 active low data carrier detect inputs for the serial port. handshake signal which notifies the uart that carrier signal is detected by the modem. the cpu can monitor the status of ndcd signal by reading bit 7 of modem status register (msr). a ndcd signal state change from low to high after the last msr read will set msr bit 3 to a 1. if bit 3 of interrupt enable register is set, the interrupt is generated when ndcd changes state. note: bit 7 of msr is the complement of ndcd. i vcc n/a 54 ndsr1 active low data set ready inputs for the serial port. handshake signal, which notifies the uart that the modem is ready to establish the communication link. the cpu can monitor the status of ndsr signal by reading bit 5 of modem status register (msr). a ndsr signal state change from low to high after the last msr read will set msr bit 1 to a 1. if bit 3 of interrupt enable register is set, the interrupt is generated when ndsr changes state. note: bit 5 of msr is the complement of ndsr. i vcc n/a 52 rxd1 receiver serial data input for port 1. is vcc n/a table 4-1: pin functions (continued) stqfp pin # name description buffer name input buffer power well output buffer power well notes
? 2005 - 2015 microchip technology inc. ds00002020a-page 9 SIO1007 55 nrts1 (sysopt0) active low request to send outputs for the serial port. handshake output signal notifies modem that the uart is ready to transmit data. this signal can be programmed by writing to bit 1 of the modem control register (mcr). the hardware reset will reset the nrts signal to inactive mode (high). nrts is forced inactive during loop mode operation. at the deasserting edge of pcirst#, the nrts pin is latched to determine the configuration base address: 0 = index base i/o address bits a[7:0]= 2e hex; 1 = index base i/o address bits a[7:0]==4e hex. o8 n/a vcc 4-2 53 txd1 transmit serial data output for port 1. o12 n/a vcc 56 ncts1 active low clear to send inputs for the serial port. handshake signal which notifies the uart that the modem is ready to receive data. the cpu can monitor the status of ncts signal by reading bit 4 of modem status register (msr). a ncts signal state change from low to high after the last msr read will set msr bit 0 to a 1. if bit 3 of the interrupt enable register is set, the interrupt is generated when ncts changes state. the ncts signal has no effect on the transmitter. note: bit 4 of msr is the complement of ncts. i vcc n/a 57 ndtr1 (sysopt1) active low data terminal ready outputs for the serial port. handshake output signal notifie s modem that the uart is ready to establish data communication link. this signal can be programmed by writing to bit 0 of modem control register (mcr). the hardware reset will reset the ndtr signal to inactive mode (high). ndtr is forced inactive during loop mode operation. at the deasertting edge of pcirst#, the ndtr1 pin is latched to determine the configuration base address: 0 = index base i/o address bits a[15:8]=00 hex; 1 = index base i/o address bits a[15:8]= 16 hex. op14 n/a vcc 4-2 table 4-1: pin functions (continued) stqfp pin # name description buffer name input buffer power well output buffer power well notes
SIO1007 ds00002020a-page 10 ? 2005 - 2015 microchip technology inc. 58 nri1 active low ring indicator inputs for the serial port. handshake signal which notifies the uart that the telephone ring signal is detected by the modem. the cpu can monitor the status of nri signal by reading bit 6 of modem status register (msr). a nri signal state change from low to high after the last msr read will set msr bit 2 to a 1. if bit 3 of interrupt enable register is set, the interrupt is generated when nri changes state. note: bit 6 of msr is the complement of nri. ivtrn/a infrared interface (3) 50 irrx2 ir receive is vtr 49 irtx2 ir transmit o12 vcc 51 irmode/ irrx3 ir mode.ir receive 3. o6/ is vtr vtr miscellaneous (34) 34 gp15 /cirrx dedicated general purpose input/output. consumer ir receiver is/o8/od8/ is vtr vcc 4-4 35 gp16 /cirtx dedicated general purpose input/output. consumer ir transmitter io12/od12/ o12 vtr vcc 4-4 4-5 27,28,3 4,35,36, 38,39,4 9,41,43, 44,46,6 1 gp10,gp11 gp15-gp17 gp30-gp37 dedicated general purpose input/output. io8/od8 vtr vcc 4-4 30 gp12/ nio_smi general purpos e input/output. active low system management interrupt output. i(i/o12/od12 ) /(o12/od12 vtr, vcc 4-4 32 gp13/ irqin1/ clki32 general purpos e input/output. external interrupt input. steerable onto one of the 15 serial irqs. 32khz suspend clock input. (is/o8/od8)/ is is vtr vcc 4-4 33 gp14/ irqin2 general purpos e input/output. external interrupt input. steerable onto one of the 15 serial irqs. (i/o8/od8)/ i vtr, vcc vcc 4-4 47 nio_pme this active low power management event signal allows this device to request wakeup. (o12/od12) vtr note: the ?n? as the first letter of a signal name or the ?# ? as the suffix of a signal name indicates an ?active low? signal. table 4-1: pin functions (continued) stqfp pin # name description buffer name input buffer power well output buffer power well notes
? 2005 - 2015 microchip technology inc. ds00002020a-page 11 SIO1007 note 4-1 the lpcpd# pin may be tied high. the lpc interfac e will function properly if the pci_reset# signal follows the protocol defined for the lreset# signal in the "low pin count interface specification". note 4-2 the nrts1/sysopt0 and the ndts1/sysopt1 pins require extern al pullup/pull-down resistors to set the default base i/o address for configuration to 0x002e, 0x004e, 0x162e, or 0x164e. note 4-3 the lpc interface pins are 3.3 v only. these signals meet pci dc specifications for 3.3v signaling. these pins are not 5v tolerant and do not have chiprotect. note 4-4 these pins have an internal 45ua pull-up that is on ly active when the programmed via the gpio pull- up registers (cr37-cr38). the default state for the pin is for the pull-up to be enabled. note 4-5 iif cirtx signal function is used and interfaced to a transceiver requiring duty cycle protection, an external 5kohm pulldown resistor should be used. in addition the an internal 45a pullup resistor on the cirtx pin should be disabled by clearing the the gp16 bit in cr38 on page 82 . 4.2 buffer type description note 4-6 see the ?pci local bus specificat ion,? revision 2.1, section 4.2.2. note 4-7 see the ?pci local bus specification,? revision 2.1, section 4.2.2 and 4.2.3. note: the buffer type values are specified at vcc=3.3v. table 4-2: buffer types buffer type description i input, ttl compatible. is input with schmitt trigger. o6 output, 6ma sink, 3ma source. o8 output, 8ma sink, 4ma source. od8 open drain output, 8ma sink. io8 input/output, 8ma sink, 4ma source. is/o8 input with schmitt trigger /output, 8ma sink, 4ma source. o12 output, 12ma sink, 6ma source. od12 open drain output, 12ma sink. io12 input/output, 12ma sink, 6ma source. op14 output, 14ma sink, 14ma source. o24 output, 24ma sink, 12ma source. pci_io input/output. these pins must meet the pci 3.3v ac and dc characteristics. ( note 4-6 ) pci_o output. these pins must meet the pc i 3.3v ac and dc characteristics. ( note 4-6 ) pci_i input. these pins must meet the pci 3.3v ac and dc characteristics. ( note 4-6 ) pci_iclk clock input. these pins must meet the pci 3.3v ac and dc characteristics and timing. ( note 4-7 )
SIO1007 ds00002020a-page 12 ? 2005 - 2015 microchip technology inc. 5.0 power functionality the SIO1007 has two power planes: vcc and vtr. the SIO1007 is a 3.3 volt part. both the vcc and vtr supply are 3.3 volts (nominal). see the operational description section and the maximum current values subsection. 5.1 3.3 volt operation / 5 volt tolerance the SIO1007 is a 3.3 volt part. it is intended solely for 3.3v applications. non-lpc bus pins are 5v tolerant and chipro- tect. a 5v tolerant pin input voltage is 5.5v max, and t he i/o buffer output pads are backdrive protected. chiprotect ? pins can be connected to a powered up external input or output device when the SIO1007 is unpowered. for example, this includes an external de vice outputting a high to an unpowered pin if the voltage does not exceed the max- imum ratings, positive voltage on any pin, with respect to ground parameter (+5.5v). see table 4-1 and the associated note 4-4 to identify the non-5v tolerant pins. 5.2 vtr support the SIO1007 requires a trickle supply (v tr ) to provide sleep current for the programmable wake-up events in the pme interface when v cc is removed. if the SIO1007 is not intended to provide wake-up capabilities on standby current, v tr can be connected to v cc . the v tr pin generates a v tr power-on-reset signal to initialize these components. 5.3 internal pwrgood an internal pwrgood logical control is included to minimize the effects of pin-state uncerta inty in the host interface as v cc cycles on and off. when the internal pwrgood signal is ?1? (active), v cc > 2.3v (nominal), and the SIO1007 host interface is active. when the internal pwrgood signal is ?0? (inactive), v cc ? 2.3v (nominal), and the SIO1007 host interface is inactive; that is, lpc bus reads and writes will not be decoded. the SIO1007 device pins io_pme#, nri1, irrx2, irtx2, ir mode/irrx3 and all gpios (as i nput) are part of the pme interface and remain active when the internal pwrgood signal has gone inactive, provided v tr is powered. see trickle power functionality section. 5.4 trickle power functionality when the SIO1007 is running under vtr only, the pme wakeup events are active and (if enabled) able to assert the io_pme# pin active low. the following lists the wakeup events: ? uart 1 ring indicator ? ir receive (irrx2) ? circc2 block ? gpios for wakeup. see below. the following requirements apply to all i/o pins that are specified to be 5 volt tolerant. ? i/o buffers that are wake-up event compatible are powe red by vcc. under vtr power (vcc=0), these pins may only be configured as inputs. these pins have input buffers into the wakeup logic that are powered by vtr. ? i/o buffers that may be configured as either push-pu ll or open drain under vtr power (vcc=0), are powered by vtr. this means they will, at a minimum, source thei r specified current from vt r even when vcc is present. note: if v tr is to be used for programmable wake-up events when v cc is removed, v tr must be at its full mini- mum potential at least 10 ? s before v cc begins a power-on cycle. when v tr and v cc are fully powered, the potential difference between the tw o supplies must not exceed 500mv. note: the gp13/irqin1/clki32 pin must be connected to a 32khz suspend clock source (i.e., available under vtr and the clki32 alternate function programmed on the gp13/irqin1/clki32 pin) for the nec ppm and rc5 wake events to be operational.
? 2005 - 2015 microchip technology inc. ds00002020a-page 13 SIO1007 the gpios that are used for pme wa keup inputs are gp10-gp17, gp20-gp 24, gp30-gp37. these gpios function as follows: ? buffers are powered by vcc, but in the absence of v cc they are backdrive protected (they do not impose a load on any external vtr powered circuitry). they are wakeup compatible as inputs under vtr power. these pins have input buffers into the wakeup logic that are powered by vtr. all gpios listed above are for pme wakeup as a gpio function (or alternate function). see the table in the gpio section for more information. the following list summarizes the blocks, re gisters and pins that are powered by vtr. ? pme interface block ? runtime register block (includes all pme, smi, gp data registers) ? pins for pme wakeup: gpios (gp10-gp17, gp30-gp37) io_pme# nri1, irrx2 5.5 maximum current values see the operational description section for the maximum current values. the maximum vtr current, i tr , is given with all outputs open (not loaded), a nd all inputs in a fixed state (i.e., 0v or 3.3v). the total maximum current for the part is the unloade d value plus the maximum curr ent sourced by the pin that is driven by vtr. the pin that is powered by vtr (as output) is io_pme#. this pin, if configured as a push-pull output, will source a minimum of 6ma at 2.4v when driving. the maximum vcc current, i cc , is given with all outputs open (not loaded), and all inputs in a fixed state (i.e., 0v or 3.3v). 5.6 power management events (pme/sci) the SIO1007 offers support for power management events (pme s), also referred to as syst em control interrupt (sci) events. the terms pme and sci are used synonymously througho ut this document to refer to the indication of an event to the chipset via the assertion of the nio_pme output signal. see the pme support section.
SIO1007 ds00002020a-page 14 ? 2005 - 2015 microchip technology inc. 6.0 super i/o registers the address map, shown below in ta b l e 6 - 1 , shows the addresses of the different blocks of the super i/o immediately after power up. the base addresses of the following blocks can be moved via the configuration registers: serial port com 1, serial port com 2, synchronous communications engine (sce), circc2, runtim e registers, configuration, lpc docking. some addresses are used to access more than one register. 6.1 host processor interface (lpc) the host processor communicates with the SIO1007 through a series of read/write registers via the lpc interface. the port addresses for these registers are shown in ta b l e 6 - 1 . register access is accompli shed through i/o cycles or dma transfers. all registers are 8 bits wide. section 18.5, "logical device base i/o address and range," on page 85 for base address, activation and power control for each logical device. note 1: refer to the configuration register descriptions for setting the base address. 2: serial port com 2 block provides ir support (fir and cir) but does not have standard 8 pin uart inter- face. 3: the runtime register block includes all pme, smi, and gp data registers. table 6-1: super i/o block addresses address block name notes base+(0-7) serial port com 1 ace:base1+(0-7) sce:base2+(0-7) serial port com 2 sce ir support fir and cir base+(0-7) circc2 consumer ir support nec ppm and rc5 base + (0-f) runtime registers base + (0-1) configuration base + 0 lpc docking
? 2005 - 2015 microchip technology inc. ds00002020a-page 15 SIO1007 7.0 lpc interface the following sub-sections specify the implementation of the lpc bus. 7.1 lpc interface signal definition the signals required for the lpc bus interface are described in the table below. lpc bus signals use pci 33mhz elec- trical signal characteristics. lpc cycles the following cycle types are su pported by the lpc protocol. the SIO1007 ignores cycles that it does not support. field definitions the data transfers are based on specific fields that are used in various combinat ions, depending on the cycle type. these fields are driven onto the lad[3:0] signal lines to communicate address, control and data information over the lpc bus between the host and the SIO1007. see the low pin count (lpc) interface specification revision 1.0 from intel, section 4.2 for definition of these fields. lframe# usage lframe# is used by the host to indicate the start of cycle s and the termination of cycles due to an abort or time-out condition. this signal is to be used by the SIO1007 to know w hen to monitor the bus for a cycle. this signal is used as a general notificat ion that the lad[3:0] lines contain information relative to the start or stop of a cycle, and that the SIO1007 monitors the bus to determine whether the cycle is intended for it. the use of lframe# allows the SIO1007 to enter a lower power state internally. there is no need for the SIO1007 to monitor the bus when it is inactive, so it can decouple its state mach ines from the bus, and internally gate its clocks. when the SIO1007 samples lframe# active, it immediately stops driving the lad[3:0] si gnal lines on the next clock and monitor the bus for new cycle info rmation. the lframe# signal functions as described in the low pin count (lpc) interface specification revision 1.0. i/o read and write cycles the SIO1007 is the target for i/o cycles. i/o cycles are initiated by the host for register or fifo a ccesses, and will gen- erally have minimal sync times. the minimum number of wait-states between bytes is 1. data transfers are assumed to be exactly 1-byte. if the cpu requested a 16 or 32-bit transfer, the host will break it up into 8-bit transfers. signal name type description lad[3:0] i/o lpc address/data bus. mult iplexed command, address and data bus. lframe# input frame signal. i ndicates start of new cycle a nd termination of broken cycle pci_reset# input pci reset. used as lpc interface reset. ldrq# output encoded dma/bus master request for the lpc interface. io_pme# od power mgt event signal. allo ws the SIO1007 to request wakeup. lpcpd# input powerdown signal. indicates that the si o1007 should prepare for power to be shut on the lpc interface. ser_irq i/o serial irq. pci_clk input pci clock. clkrun# i/od clock run. allows the SIO1007 to request the stopped pci_clk be started. cycle type transfer size i/o write 1 byte i/o read 1 byte dma write 1 byte dma read 1 byte
SIO1007 ds00002020a-page 16 ? 2005 - 2015 microchip technology inc. see the low pin count (lpc) interface specification reference, section 5.2, for the sequence of cycles for the i/o read and write cycles. dma read and write cycles dma read cycles involve the transfer of data from the host (main memory) to the sio10 07. dma write cycles involve the transfer of data from the SIO1007 to the host (main memo ry). data will be coming from or going to a fifo and will have minimal sync times. data tran sfers to/from the SIO1007 are 1 byte. see the low pin count (lpc) interface specification reference, section 6.4, for the field definitions and the sequence of the dma read and write cycles. dma protocol dma on the lpc bus is handled through the use of the ldrq# lines from the SIO1007 and special encodings on lad[3:0] from the host. the dma mechanism for the lpc bus is described in the low pin count (lpc) specification revision 1.0. 7.1.1 power management clockrun protocol see the low pin count (lpc) interface specification reference, section 8.1. lpcpd protocol the SIO1007 will function properly if the nlpcpd signal goes active and then inactive again without npci_reset becoming active. this is a requirement fo r notebook power management functions. although the lpc bus spec 1.0 section 8.2 states, "after lpcpd# goes back inactive, the lpc i/f will always be reset using lrst#?, this statement does not apply for mobile systems. lrst# (pci_reset#) will no t occur if the lpc bus power was not removed. for example, when exiting a "light" sleep state (a cpi s1, apm pos), lrst# (pci_reset#) will not occur. when exiting a "deeper" sleep state (acpi s3-s5, apm str, std, soft-off), lrst# (pci_reset#) will occur. the lpcpd# pin is implemented as a ?local? powergood for the lpc bus in the SIO1007. it is not used as a global pow- ergood for the chip. it is used to reset the lpc block and hold it in reset. an internal powergood is implemented in SIO1007 to minimize power dissipation in the entire chip. prior to going to a low-power state, th e system will assert the lpcpd# signal. it will go active at least 30 microseconds prior to the lclk# (pci_clk) signal stopping low and power being shut to the other lpc i/f signals. upon recognizing lpcpd# active, the SIO1007 will drive the ldrq# signal low or tri- state, and do so until lpcpd# goes back inactive. upon recognizing lpcpd# inactive, the SIO1007 will drive its ldrq# signal high. see the low pin count (lpc) interface specification reference, section 8.2. sync protocol see the low pin count (lpc) interface specification reference, section 4.2.1.8 for a table of valid sync values. typical usage the sync pattern is used to add wait states. for read cycl es, the SIO1007 immediately drives the sync pattern upon recognizing the cycle. the host immediately drives the sync pattern for wr ite cycles. if the SIO1007 needs to assert wait states, it does so by driving 0101 or 01 10 on lad[3:0] until it is ready, at which point it will drive 0000 or 1001. the SIO1007 will choose to assert 0101 or 0110 , but not switch between the two patterns. the data (or wait state sync) will immediately follow the 0000 or 1001 value. the sync value of 0101 is intended to be used for norma l wait states, wherein the cycl e will complete within a few clocks. the SIO1007 uses a sync of 0101 for all wait st ates in a dma transfer. the sync value of 0110 is inte nded to be used where the number of wait stat es is large. this is provided for epp cycles, where the number of wait states could be quite large (> 1 microsecond). however, the SIO1007 uses a sync of 0110 for all wait states in an i/o transfer. the sync value is driv en within 3 clocks.
? 2005 - 2015 microchip technology inc. ds00002020a-page 17 SIO1007 sync timeout the sync value is driven within 3 clocks. if the host obs erves 3 consecutive cl ocks without a valid sy nc pattern, it will abort the cycle. the SIO1007 does not assume any particular timeout. when the host is driving sync, it may have to insert a very large number of wait states, depending on pci latencies and retries. sync patterns and maximum number of syncs if the sync pattern is 0101, then the host as sumes that the maximum number of syncs is 8. if the sync pattern is 0110, then no maximum number of syncs is assumed. the s io1007 has protection mechanisms to complete the cycle. sync error indication the SIO1007 reports errors via t he lad[3:0] = 1010 sync encoding. if the host was reading data from the si o1007, data will still be transferred in the next two nibbles. this data may be invalid, but it will be transferred by the si o1007. if the host was writing data to the SIO1007, the data had already been transferred. in the case of multiple byte cycles, such as dma cycles, an error sync te rminates the cycle. ther efore, if the host is transferring 4 bytes from a device, if the device returns the er ror sync in the first byte, the other three bytes will not be transferred. i/o and dma start fields i/o and dma cycles use a start field of 0000. reset policy the following rules govern the reset policy: 1. when pci_reset# goes inactive (high), the clock is assumed to have been running for 100usec prior to the removal of the reset signal, so that ev erything is stable. this is the same reset active time after clock is stable that is used for the pci bus. 2. when pci_reset# go es active (low): a) the host drives the lframe# signal high, tristates the lad[3:0] signals, and ignores the ldrq# signal. b) the SIO1007 ignores lframe#, tristate the lad[3:0] pins and drive the ldrq# signal inactive (high). 7.1.2 lpc transfers wait state requirements i/o transfers the SIO1007 inserts three wait states for an i/o read and two wait states for an i/o write cycle. a sync of 0110 is used for all i/o transfers. the exception to this is for transfer s where iochrdy would be deasserted in an isa transfer (i.e., ircc transfers) in which case the sync pattern of 0110 is us ed and a large number of syncs may be inserted (up to 330 which corresponds to a timeout of 10us). dma transfers the SIO1007 inserts three wait states for a dma read and four wait states for a dma write cycle. a sync of 0101 is used for all dma transfers. see the example timing fo r the lpc cycles in the timing diagrams section.
SIO1007 ds00002020a-page 18 ? 2005 - 2015 microchip technology inc. 8.0 lpc portswitch the SIO1007 portswitch ? interface provides a hot-switchable docking lpc interface available to an external super i/o device contained within a docking station. the docking lpc bus signals, when enabled, will be routed through low impedance ( ? 10 ? ), bi-directional switches contained in the sio 1007. the SIO1007 controls the enabling of the lpc docking interface. when the SIO1007 lpc docking interface is enabled, the SIO1007 autonomously blocks all trusted lpc cycles while forwarding all standard lpc cycles to the lpc docking interface. a switchable pciclk is available to be supplied to an external devices contained within a docking station. the SIO1007 docking pciclk output is a low skewed switched version of the input. which, when enabled, is routed through low impedance ( ? 10 ? ), bi-directional switch contained in the sio100 7. the SIO1007 controls the enabling of the docking pciclk output. a switchable 14.318mhz clock is available to external devices contained within a docking station. the SIO1007 docking 14.318mhz clock output is a buffered version of the inpu t. the SIO1007 controls the enabling of the docking 14mhz clock output. see figure 8-1 .for an illustration of a system level do cking solution using the lpc portswitch ? interface. 8.1 lpc portswitch interface the signals to be switched in the lp c portswitch interface are shown in table 8-1 . all signals except sio_14m and dsio_14m are 3.3v only. sio_14m and dsio_14m are 5 volt tolerant. figure 8-1: docking solution using the lpc portswtich ? interface lpc host lpc peripheral lpc docking switch docking connector system lpc master notebook ports dock ports notebook docking station primary super i/o docking super i/o control register lpc bus (lad{3:0], lframe#, ldrq0#, ldrq1#, serirq, clkrun#, lreset#) switched lpc bus (dlad[3:0], dlframe#, dldrq1#, dserirq, dclkrun#) clock driver enb 14mhz 33mhz switch 14mhz buffer lpc_clk_33 sio_14m dlpc_clk_33 dsio_14m pciclk
? 2005 - 2015 microchip technology inc. ds00002020a-page 19 SIO1007 application note: the system design must inclu de weak pullup resistors in the docking station (~100kohm) on the dlad[3:0] and dlframe# signals to maintain an inactive docking lpc interface. 8.2 portswitch docking controls the SIO1007 provides three programmable bits which indepen dently control the switching of the 14.318mhz clock and the dedicated docking pciclk and the remainder of the lpc interface. the switching is provided in the docking lpc switch register described in section 8.3.1 . 8.3 registers 8.3.1 logical device for lpc docking. the lpc docking base address registers (cr3b and cr3c) ar e used to select the base address of lpc docking run- time register space. valid addresses for lpc docking runt ime register space can be set to locations on single-byte boundaries from 100h - fffh. to disable lpc docking runtim e register decoding, set the docking activate register (cr3a)-bit 3 to ?0?. when writing the lpc docking base a ddress registers (cr3b and cr3a) the set lpc docking acti- vate register (cr3a) -bit 3 must be set to ?0?. for detailed description of the lpc docking activate regi ster (cr3a) and the lpc docking base address registers (cr3b and cr3c.) see section 18.0 for details description of configuration registers. 8.3.2 docking lpc switch register the docking lpc switch register controls the connec tion and disconnection of the docking lpc interface. dlpc_switch ? d0 when dlpc switch is asserted ?1?, the bi-directional do cking lpc switches will be switched on and the dlpc pin connections will be connected to the lpc bus. when dlpc sw itch is deasserted ?0?, the dlpc pin connections will be disconnected from the lpc bus. table 8-1: lpc docking interface host side interface dock side interface switch control bit lad[3:0] dlad[3:0] dlpc_switch lframe# dlframe# dlpc_switch ldrq1# dldrq1# dlpc_switch nclkrun ndclkrun dlpc_switch ser_irq ser_irq dlpc_switch lpc_clk_33 dlpc_clk_33 dclk_33 sio_14m dsio_14m dclk_14 table 8-2: docking lpc switch register address dlpc runtime registers base address + 0 power vcc default 00h d7 d6 d5 d4 d3 d2 d1 d0 type r rrrrrr r/w bit name reserved dclk_1 4 dclk_3 3 dlpcswitch
SIO1007 ds00002020a-page 20 ? 2005 - 2015 microchip technology inc. dclk_33? d1 when dclk_33 bit is asserted ?1?, the bi-directional switch for the dedicated docking pciclk will be switched on and the dlpc_clk_33 pin will be connected to the lpc_clk_33 pin. when dclk_33 bit is deasserted ?0?, the dlpc_- clk_33 pin will be disconnected from the lpc_clk_33 pin and the dlpc_clk_33 pin will be an open circuit. dclk_14? d2 when dclk_14 bit is asserted ?1?, the buffer is enabl ed and the dsio_14m pin will provide a buffered version dsio_14m pin. when dclk_14 bit is deassert ed ?0?, the dsio_14m pin will be tri-stated. note: the pciclk signals are not bi-directional however, the switch only provides a low series impedance ( ? 10 ? ).
? 2005 - 2015 microchip technology inc. ds00002020a-page 21 SIO1007 9.0 serial port (uart) the SIO1007 incorporates one 8-pin 16c550a compatible ua rt. in addition, the SIO1007 provides an second uart supporting a serial infrared interface that complies with irda v1.2 (fast ir), hpsir, and askir formats (used by sharp and other pdas), as well as consumer ir. see section 10.0 , for description of infrared interface. the SIO1007 incorporates two full func tion uarts. they are compatible with the 16450, the 16450 ace registers and the 16c550a. the uarts perform serial-to-parallel conversion on received characters and parallel-to-serial conversion on transmit characters. the data rates are independently pr ogrammable from 460.8k baud down to 50 baud. the char- acter options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. the uarts each contain a programmable baud rate generator th at is capable of dividing the input clock or crystal by a number from 1 to 65535. the uarts are also capable of supp orting the midi data rate. re fer to the configuration reg- isters for information on disabling, power down and changing the base address of the uart s. the interrupt from a uart is enabled by programming out2 of that uart to a logic "1 ". out2 being a logic "0" disables that uart's interrupt. the second uart also supports irda 1.2 (4mbps), hp-s ir, ask-ir and consumer ir infrared modes of operation. 9.1 register description addressing of the accessible registers of the serial port is shown below. the base addresses of the serial ports are defined by the configur ation registers (see configuration section). the serial port regi sters are located at sequentially increasing addresses above these base addresses. the SIO1007 contains two serial ports, each of which contain a register set as described below. note 9-1 dlab is bit 7 of the line control register the following section describes the operation of the registers. 9.1.1 receive buffer register (rb) address offset = 0h, dlab = 0, read only this register holds the received incoming data byte. bit 0 is the least significant bit, which is transmitted and received first. received data is double buffered; this uses an additional shift register to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the re ceive buffer register. the shift register is not accessible. 9.1.2 transmit buff er register (tb) address offset = 0h, dlab = 0, write only this register contains the data byte to be transmitted. t he transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data word to a serial format. this shift register is loaded from the transmit buffer when the transmission of the previous byte is complete. table 9-1: addressing the serial port dlab ( note 9-1 ) a2 a1 a0 register name 0 0 0 0 receive buffer (read) 0 0 0 0 transmit buffer (write) 0 0 0 1 interrupt enable (read/write) x 0 1 0 interrupt identification (read) x 0 1 0 fifo control (write) x 0 1 1 line control (read/write) x 1 0 0 modem control (read/write) x 1 0 1 line status (read/write) x 1 1 0 modem status (read/write) x 1 1 1 scratchpad (read/write) 1 0 0 0 divisor lsb (read/write) 1 0 0 1 divisor msb (read/write
SIO1007 ds00002020a-page 22 ? 2005 - 2015 microchip technology inc. 9.1.3 interrupt enabl e register (ier) address offset = 1h, dlab = 0, read/write the lower four bits of this register cont rol the enables of the five interrupt sources of the serial port interrupt. it is poss ible to totally disable the interrupt system by resetting bits 0 thr ough 3 of this register. simila rly, setting the appropriate bits of this register to a high, selected interrupts can be enabl ed. disabling the interrupt system inhibits the interrupt identi- fication register and dis ables any serial port interrupt out of the SIO1007. all other syst em functions operate in their normal manner, including the line status and modem status registers. the contents of the interrupt enable register are described below. bit 0 this bit enables the received data available interrupt (and timeout interrupts in the fifo mode) when set to logic "1". bit 1 this bit enables the transmitter holding register empty interrupt when set to logic "1". bit 2 this bit enables the received line status interrupt when se t to logic "1". the error sources causing the interrupt are overrun, parity, framing and break. the line status register must be read to determine the source. bit 3 this bit enables the modem status interrupt when set to logic "1". this is caused when one of the modem status reg- ister bits changes state. bits 4 through 7 these bits are always logic "0". 9.1.4 fifo control register (fcr) address offset = 2h, dlab = x, write this is a write only regi ster at the same location as the ii r. this register is used to enable and clear the fifos, set the rcvr fifo trigger level. bit 0 setting this bit to a logic "1" enables both the xmit and rcvr fifos. clearing this bit to a logic "0" disables both the xmit and rcvr fifos and clears all bytes from both fifos. when changing from fi fo mode to non-fifo (16450) mode, data is automatically cleared from the fifos. this bi t must be a 1 when other bits in this register are written to or they will not be properly programmed. bit 1 setting this bit to a logic "1" clears all bytes in the rcvr fifo and resets its counter logic to 0. the shift register is not cleared. this bit is self-clearing. bit 2 setting this bit to a logic "1" clears all bytes in the xmit fi fo and resets its counter logic to 0. the shift register is not cleared. this bit is self-clearing. bit 3 writing to this bit has no effect on the operation of the uart. dma modes are not supported in this chip. bit 4,5 reserved bit 6,7 these bits are used to set the trigger level for the rcvr fifo interrupt. note: dma is not supported. the uart1 and uart2 fcr? s are shadowed in the uart1 fifo control shadow register (cr15) and uart2 fifo cont rol shadow register (cr16). see the configuration section for description on these registers.
? 2005 - 2015 microchip technology inc. ds00002020a-page 23 SIO1007 9.1.5 interrupt identification register (iir) address offset = 2h, dlab = x, read by accessing this register, the host cpu can determine the highes t priority interrupt and its source. four levels of priority interrupt exist. they are in descending order of priority: 1. receiver line status (highest priority) 2. received data ready 3. transmitter holding register empty 4. modem status (lowest priority) information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the interrupt iden - tification register (refer to interrupt control table). when t he cpu accesses the iir, the serial port freezes all interrupts and indicates the highest priority pending interrupt to the cpu. during this cpu access, even if the serial port records new interrupts, the current indication does not change until access is completed. the contents of the iir are described below. bit 0 this bit can be used in either a hardwired prioritized or po lled environment to indicate whether an interrupt is pending. when bit 0 is a logic "0", an interrupt is pending and the cont ents of the iir may be used as a pointer to the appropriate internal service routine. when bit 0 is a logic "1", no interrupt is pending. bits 1 and 2 these two bits of the iir are used to id entify the highest priority interrupt pending as indicated by the interrupt control table. bit 3 in non-fifo mode, this bit is a logic "0". in fifo mode this bit is set along with bit 2 when a timeout interrupt is pending. bits 4 and 5 these bits of the iir are always logic "0". bits 6 and 7 these two bits are set when the fifo control register bit 0 equals 1. bit 7 bit 6 rcvr fifo trigger level (bytes) 00 1 01 4 10 8 11 14
SIO1007 ds00002020a-page 24 ? 2005 - 2015 microchip technology inc. 9.1.6 line control register (lcr) address offset = 3h, dlab = 0, read/write this register contains the format information of the serial line. the bit definitions are: bits 0 and 1 these two bits specify the number of bits in each transmitte d or received serial character. the encoding of bits 0 and 1 is as follows: the start, stop and parity bits are not included in the word length. table 9-2: interrupt control table fifo mode only interrupt identification register interrupt set and reset functions bit 3 bit 2 bit 1 bit 0 priority level interrupt type interrupt source interrupt reset control 0 0 0 1 - none none - 0 1 1 0 highest receiver line status overrun error, parity error, framing error or break interrupt reading the line status register 0 1 0 0 second received data available receiver data available read receiver buffer or the fifo drops below the trigger level. 1 1 0 0 second character timeout indication no characters have been removed from or input to the rcvr fifo during the last 4 char times and there is at least 1 char in it during this time reading the receiver buffer register 0010thirdtransmitter holding register empty transmitter holding register empty reading the iir register (if source of interrupt) or writing the transmitter holding register 0 0 0 0 fourth modem status clear to send or data set ready or ring indicator or data carrier detect reading the modem status register figure 9-1: serial data bit 1 bit 0 word length 0 0 1 1 0 1 0 1 5 bits 6 bits 7 bits 8 bits
? 2005 - 2015 microchip technology inc. ds00002020a-page 25 SIO1007 bit 2 this bit specifies the number of stop bits in each transm itted or received serial character. the following table summa- rizes the information. bit 3 parity enable bit. when bit 3 is a logic "1", a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and the first stop bit of the serial da ta. (the parity bit is used to generate an even or odd number of 1s when the data word bits and the parity bit are summed). bit 4 even parity select bit. when bit 3 is a logic "1" and bit 4 is a logic "0", an odd number of logic "1"'s is transmitted or checked in the data word bits and the parity bit. when bit 3 is a logic "1" and bit 4 is a logic "1" an even number of bits is transmitted and checked. bit 5 stick parity bit. when parity is enabled it is used in conjuncti on with bit 4 to select mark or space parity. when lcr bits 3, 4 and 5 are 1 the parity bit is transmitted and checked as 0 (space parity). if bits 3 and 5 are 1 and bit 4 is a 0, then the parity bit is transmitted and checked as 1 (mark parity). if bit 5 is 0 stick parity is disabled. bit 6 set break control bit. when bit 6 is a logic "1", the transmit data output (txd) is forced to the spacing or logic "0" state and remains there (until reset by a low level bit 6) regardless of other transmitter activity. this feature enables the serial port to alert a terminal in a communications system. bit 7 divisor latch access bit (dlab). it must be set high (logic "1 ") to access the divisor latches of the baud rate generator during read or write operations. it must be set low (logic "0") to access th e receiver buffer register, the transmitter holding register, or the interrupt enable register. 9.1.7 modem control register (mcr) address offset = 4h, dlab = x, read/write this 8-bit register controls the inte rface with the modem or data set (or de vice emulating a modem). the contents of the modem control regist er are described below. bit 0 this bit controls the data terminal ready (ndtr) output. when bit 0 is set to a logic "1", the ndtr output is forced to a logic "0". when bit 0 is a logic "0", the ndtr output is forced to a logic "1". bit 1 this bit controls the request to send (nrts) output. bit 1 affects the nrts output in a manner identical to that described above for bit 0. bit 2 this bit controls the output 1 (out1) bit. this bit does not have an output pin and can only be read or written by the cpu. bit 3 output 2 (out2). this bit is used to enable an uart interrupt . when out2 is a logic "0", the serial port interrupt output is forced to a high impedance state - disabled. when out2 is a logic "1", the serial port interrupt outputs are enabled. bit 2 word length number of stop bits 0 -- 1 15 bits 1.5 16 bits 2 17 bits 2 18 bits 2 note: the receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting.
SIO1007 ds00002020a-page 26 ? 2005 - 2015 microchip technology inc. bit 4 this bit provides the loopback feature for diagnostic testing of the serial port. when bit 4 is set to logic "1", the following occur: 1. the txd is set to the marking state (logic "1"). 2. he receiver serial input (rxd) is disconnected. 3. the output of the transmitter shift register is "looped back" into the receiver shift register input. 4. all modem control inputs (ncts, ndsr, nri and ndcd) are disconnected. 5. the four modem control outputs (ndtr, nrts, out1 and out2) are internally connected to the four modem control inputs (ndsr, ncts, ri, dcd). 6. the modem control output pins are forced inactive high. 7. data that is transmitted is immediately received. this feature allows the processor to ve rify the transmit and receive data paths of the serial port. in the diagnostic mode, the receiver and the transmitter interrupts are operational. the modem control interrupts are also operational but the interrupts' sources are now the lower four bits of the mo dem control register instead of the modem control inputs. the interrupts are still controlled by the interrupt enable register. bits 5 through 7 these bits are permanently set to logic zero. 9.1.8 line status register (lsr) address offset = 5h, dlab = x, read/write bit 0 data ready (dr). it is set to a logic "1" whenever a co mplete incoming character has been received and transferred into the receiver buffer register or the fifo. bit 0 is reset to a logic "0" by reading all of the data in the receive buffer register or the fifo. bit 1 overrun error (oe). bit 1 indicates that data in the receiver buffer register was not read before the next character was transferred into the register, thereby de stroying the previous character. in fifo mode, an overrun error will occur only when the fifo is full and the next character has been completely received in the shift register, the character in the shift register is overwritten but not transferred to the fifo. the oe indicator is set to a logic "1" immediately upon detection of an overrun condition, and reset whenev er the line status register is read. bit 2 parity error (pe). bit 2 indica tes that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. the pe is set to a logic "1" upon detection of a parity error and is reset to a logic "0" whenever the line status register is read. in the fifo mode, this error is associated with the part icular character in the fifo it applies to. this error is indicated when the associated character is at the top of the fifo. bit 3 framing error (fe). bit 3 indicates that the received characte r did not have a valid stop bit. bit 3 is set to a logic "1" whenever the stop bit following the last data bit or parity bit is detected as a zero bit (spacing level). the fe is reset to a logic "0" whenever the line status register is read. in t he fifo mode, this error is asso ciated with the pa rticular char- acter in the fifo it applies to. this error is indicated when the associated character is at the top of the fifo. the serial port will try to resynchronize after a framing error. to do th is, it assumes that the framing error was due to the next start bit, so it samples this 'start' bit twice and then takes in the 'data'. bit 4 break interrupt (bi). bit 4 is set to a logic "1" whenever th e received data input is held in the spacing state (logic "0") for longer than a full word transmission time (that is, the tota l time of the start bit + data bits + parity bits + stop bits). the bi is reset after the cpu reads the contents of the line status register. in the fifo mode, this error is associated with the particular character in the fifo it applies to. this error is indicated when the associated character is at the top of the fifo. when break occurs only one zero character is loaded into the fifo. restarting after a break is received, requires the serial data (rxd) to be logic "1" for at least 1/2 bit time. note: bits 1 through 4 are the error conditions that produce a receiver line status interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled.
? 2005 - 2015 microchip technology inc. ds00002020a-page 27 SIO1007 bit 5 transmitter holding register empty (thre). bit 5 indicates that the serial port is ready to accept a new character for transmission. in addition, this bit causes the serial port to issue an interrupt when the transmitter holding register inter- rupt enable is set high. the thre bit is set to a logic "1" when a character is transferred from the transmitter holding register into the transmitter shift register. the bit is rese t to logic "0" whenever the cpu loads the transmitter holding register. in the fifo mode, this bit is set when the xmit fifo is empty, it is cleared when at least 1 byte is written to the xmit fifo. bit 5 is a read only bit. bit 6 transmitter empty (temt). bit 6 is set to a logic "1" whene ver the transmitter holding register (thr) and transmitter shift register (tsr) are both empty. it is reset to logic "0" whenever either the thr or tsr contains a data character. bit 6 is a read only bit. in the fifo mode this bit is set whenever the thr and tsr are both empty. bit 7 this bit is permanently set to logic "0" in the 450 mode. in t he fifo mode, this bit is set to a logic "1" when there is at least one parity error, framing error or break indication in the fifo. this bit is cleared when the lsr is read if there are no subsequent errors in the fifo. 9.1.9 modem status register (msr) address offset = 6h, dlab = x, read/write this 8-bit register prov ides the current state of the control lines from the modem (or peripheral device). in addition to this current state information, four bits of the modem status register (ms r) provide change information. these bits are set to logic "1" whenever a control input from the mode m changes state. they are reset to logic "0" whenever the modem status register is read. bit 0 delta clear to send (dcts). bit 0 indicates that the ncts input to the chip has changed state since the last time the msr was read. bit 1 delta data set ready (ddsr). bit 1 indicates that the ndsr input has changed state since the last time the msr was read. bit 2 trailing edge of ring indicator (teri). bit 2 indicates that the nri input has changed from logic "0" to logic "1". bit 3 delta data carrier detect (ddcd). bit 3 indicates th at the ndcd input to the chip has changed state. bit 4 this bit is the complement of the clear to send (ncts) input. if bit 4 of the mcr is set to logic "1", this bit is equivalent to nrts in the mcr. bit 5 this bit is the complement of the data set ready (ndsr) input. if bit 4 of the mcr is set to logic "1", this bit is equivalent to dtr in the mcr. bit 6 this bit is the complement of the ring indicator (nri) input. if bi t 4 of the mcr is set to logic "1", this bit is equivalent t o out1 in the mcr. bit 7 this bit is the complement of the data carrier detect (ndcd) input. if bit 4 of the mcr is set to logi c "1", this bit is equivalent to out2 in the mcr. note: whenever bit 0, 1, 2, or 3 is set to a logi c "1", a modem status interrupt is generated.
SIO1007 ds00002020a-page 28 ? 2005 - 2015 microchip technology inc. 9.1.10 scratchpad register (scr) address offset =7h, dlab =x, read/write this 8-bit read/write register has no effect on the operation of the serial port. it is inte nded as a scratchpad register to be used by the programmer to hold data temporarily. 9.2 programmable baud rate generator (and divisor latches dlh, dll) the serial port contains a programmable baud rate generator that is capable of dividing the internal pll clock by any divisor from 1 to 65535. the internal pll clock is divided down to generate a 1.8462mhz frequency for baud rates less than 38.4k, a 1.8432mhz frequency for 115.2k, a 3.6864 mhz frequency for 230.4k and a 7.3728mhz frequency for 460.8k. this output frequency of the baud rate generator is 16x the baud rate . two 8 bit latches store the divisor in 16 bit binary format. these divisor latches must be loaded during initialization in order to insure desired operation of the baud rate generator. upon loading either of the divisor latches, a 16-bit baud counter is immediately loaded. this prevents long counts on initial load. if a 0 is loaded into t he brg registers the output divides the clock by the number 3. if a 1 is loaded, the output is the invers e of the input oscillator. if a two is l oaded the output is a divide by 2 signal with a 50% duty cycle. if a 3 or greater is loaded the output is low for 2 bits and high for the remainder of the count. the input clock to the brg is a 1.8462 mhz clock. ta b l e 9 - 3 shows the baud rates possible. 9.3 effect of the reset on register file the reset function table ( ta b l e 9 - 4 ) details the effect of the reset input on each of the registers of the serial port. 9.4 fifo interrupt mode operation when the rcvr fifo and receiver interrupts are enabled (f cr bit 0 = "1", ier bit 0 = "1"), rcvr interrupts occur as follows: a) the receive data available interrupt will be issued when the fifo has reached its prog rammed trigger level; it is cleared as soon as the fifo drops below its programmed trigger level. b) the iir receive data available indication also occurs w hen the fifo trigger level is reached. it is cleared when the fifo drops below the trigger level. c) the receiver line status interrupt (iir=06h), has highe r priority than the received data available (iir=04h) inter- rupt. d) the data ready bit (lsr bit 0) is set as soon as a ch aracter is transferred from th e shift register to the rcvr fifo. it is reset when the fifo is empty. when rcvr fifo and receiver interrupts are enabled, rcvr fifo timeout interrupts occur as follows: a) a fifo timeout interrupt occurs if all the following conditions exist: at least one character is in the fifo. the most recent serial character received was longer than 4 continuous character times ago. (if 2 stop bits are programmed, the second one is included in this time delay). the most recent cpu read of the fifo was l onger than 4 continuous character times ago. this will cause a maximum character received to interrupt issued delay of 160 msec at 300 baud with a 12-bit character. b) character times are calculated by using the rclk input for a clock signal (this makes the delay proportional to the baud rate). c) when a timeout interrupt has occurred it is cleared and the timer reset when the cpu reads one character from the rcvr fifo. d) when a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the cpu reads the rcvr fifo. when the xmit fifo and transmitter interrupts are enabled (f cr bit 0 = "1", ier bit 1 = "1"), xmit interrupts occur as follows: a) the transmitter holding register interrupt (02h) occurs when the xmit fifo is empty; it is cleared as soon as the transmitter holding register is written to (1 of 16 characters may be wr itten to the xmit fifo while servicing this interrupt) or the iir is read.
? 2005 - 2015 microchip technology inc. ds00002020a-page 29 SIO1007 b) the transmitter fifo empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: thre=1 and there have not been at leas t two bytes at the same time in the transmitter fifo since the last thre=1. the transmitter interrupt after changing fcr0 will be immediate, if it is enabled. character timeout and rcvr fifo trigger le vel interrupts have the same priority as the current received data available interrupt; xmit fifo empty has the sa me priority as the current transmit ter holding register empty interrupt. 9.5 fifo polled mode operation with fcr bit 0 = "1" resetting ier bits 0, 1, 2 or 3 or all to zero puts the uart in the fifo polled mode of operation. since the rcvr and xmitter are controlled separately, either one or both can be in the polled mode of operation. in this mode, the user's program will che ck rcvr and xmitter status via the lsr. lsr definitions for the fifo polled mode are as follows: bit 0=1 as long as there is one byte in the rcvr fifo. bits 1 to 4 specify which error(s) have occurred. character erro r status is handled the same way as when in the interrupt mode, the iir is not affected since eir bit 2=0. bit 5 indicates when the xmit fifo is empty. bit 6 indicates that both the xmit fifo and shift register are empty. bit 7 indicates whether there are any errors in the rcvr fifo. there is no trigger level reached or timeout condition indi cated in the fifo polled mode, however, the rcvr and xmit fifos are still fully capable of holding characters. note 9-2 the percentage error for all baud rates, exce pt where indicated otherwise, is 0.2%. note 9-3 the high speed bit is located in the device configuration space. table 9-3: baud rates desired baud rate divisor used to generate 16x clock percent error difference between desired and actual ( note 9-2 ) high speed bit ( note 9-3 ) 50 2304 0.001 x 75 1536 - x 110 1047 - x 134.5 857 0.004 x 150 768 - x 300 384 - x 600 192 - x 1200 96 - x 1800 64 - x 2000 58 0.005 x 2400 48 - x 3600 32 - x 4800 24 - x 7200 16 - x 9600 12 - x 19200 6 - x 38400 3 0.030 x 57600 2 0.16 x 115200 1 0.16 x 230400 32770 0.16 1 460800 32769 0.16 1
SIO1007 ds00002020a-page 30 ? 2005 - 2015 microchip technology inc. table 9-4: reset function table register/signal reset control reset state interrupt enable regi ster reset all bits low interrupt identification reg. reset bit 0 is high; bits 1 - 7 low fifo control reset all bits low line control reg. reset all bits low modem control reg. reset all bits low line status reg. reset all bits low except 5, 6 high modem status reg. reset bits 0 - 3 low; bits 4 - 7 input txd1, txd2 reset high intrpt (rcvr errs) reset/read lsr low intrpt (rcvr data ready) reset/read rbr low intrpt (thre) reset/readiir/write thr low out2b reset high rtsb reset high dtrb reset high out1b reset high rcvr fifo reset/ fcr1*fcr0/_fcr0 all bits low xmit fifo reset/ fcr1*fcr0/_fcr0 all bits low
? 2005 - 2015 microchip technology inc. ds00002020a-page 31 SIO1007 table 9-5: register summary for an individual uart channel regiser address ( note 9-4 ) register name reg. symbol bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 addr = 0 dlab = 0 receive buffer register (read only) rbr data bit 0 ( note 9-5 ) data bit 1 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 addr = 0 dlab = 0 transmitter holding register (write only) thr data bit 0 data bit 1 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 addr = 1 dlab = 0 interrupt enable register ier enable received data available interrupt (erdai) enable trans- mitter holding register empty interrupt (ethrei) enable receiver line status interrupt (elsi) enable modem status interrupt (emsi) 00 0 0 addr = 2 interrupt ident. register (read only) iir "0" if interrupt pending interrupt id bit interrupt id bit interrupt id bit ( note 9-9 ) 00 fifos enabled ( note 9-9 ) fifos enabled ( note 9-9 ) addr = 2 fifo control register (write only) fcr ( note 9-11 ) fifo enable rcvr fifo reset xmit fifo reset dma mode select ( note 9-11 ) reserved reserved rcvr trigger lsb rcvr trigger msb addr = 3 line control register lcr word length select bit 0 (wls0) word length select bit 1 (wls1) number of stop bits (stb) parity enable (pen) even parity select (eps) stick parity set break divisor latch access bit (dlab) addr = 4 modem control register mcr data terminal ready (dtr) request to send (rts) out1 ( note 9-7 ) out2 ( note 9-7 ) loop 0 0 0 addr = 5 line status register lsr data ready (dr) overrun error (oe) parity error (pe) framing error (fe) break interrupt (bi) transmitter holding register (thre) transmitter empty (temt) ( note 9-6 ) error in rcvr fifo ( note 9-9 ) addr = 6 modem status register msr delta clear to send (dcts) delta data set ready (ddsr) trailing edge ring indicator (teri) delta data carrier detect (ddcd) clear to send (cts) data set ready (dsr) ring indicator (ri) data carrier detect (dcd) addr = 7 scratch register ( note 9-8 ) scr bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 addr = 0 dlab = 1 divisor latch (ls) ddl bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 addr = 1 dlab = 1 divisor latch (ms) dlm bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15
SIO1007 ds00002020a-page 32 ? 2005 - 2015 microchip technology inc. uart register summary notes: note 9-4 dlab is bit 7 of the line control register (addr = 3). note 9-5 bit 0 is the least significant bit. it is th e first bit serially transmitted or received. note 9-6 when operating in the xt mode, this bit will be set any ti me that the transmitter shift register is empty. note 9-7 this bit no longer has a pin associated with it. note 9-8 when operating in the xt mode, th is register is not available. note 9-9 these bits are always zero in the non-fifo mode. note 9-10 writing a one to this bit has no effect. dma modes are not supported in this chip. note 9-11 the uart1 and uart2 fcr?s are shadowed in the uart1 fifo control shadow register (cr15) and uart2 fifo control shadow register (cr16). 9.6 notes on serial port operation 9.6.1 fifo mode operation general the rcvr fifo will hold up to 16 bytes regardless of which trigger level is selected. 9.6.2 tx and rx fifo operation the tx portion of the uart transmits data through txd as soon as the cpu loads a byte into the tx fifo. the uart will prevent loads to the tx fifo if it currently holds 16 characters. loading to the tx fifo will again be enabled as soon as the next character is transferred to the tx shift register. these capabilities a ccount for the largely autonomous operation of the tx. the uart starts the above operations typically with a tx inte rrupt. the chip issues a tx interrupt whenever the tx fifo is empty and the tx interrupt is enabl ed, except in the following instance. assu me that the tx fifo is empty and the cpu starts to load it. when the first byte enters the fifo the tx fifo empty inte rrupt will transition from active to inac- tive. depending on the execution speed of the service routine software, the uart may be able to transfer this byte from the fifo to the shift regist er before the cpu loads another byte. if this happens, the tx fifo will be empty again and typically the uart's interrupt line would transition to the active state. this could cause a system with an interrupt control unit to record a tx fifo empty condition, even though the cp u is currently servicing that interrupt. therefore, after the first byte has been loaded into the fifo, the uart will wait one serial character transmission time before issuing a new tx fifo empty interrupt. this one character tx interrupt de lay will remain active until at least two bytes have been loaded into the fifo, concurrently. when t he tx fifo empties after this condition, the tx interrupt will be activated with- out a one character delay. rx support functions and operation are qui te different from those described for the transmitter. the rx fifo receives data until the number of bytes in the fifo equals the selected in terrupt trigger level. at that time if rx interrupts are enabled, the uart will issue an interrupt to the cpu. the rx fifo will continue to store bytes until it holds 16 of them. it will not accept any more data when it is full. any more da ta entering the rx shift register will set the overrun error flag. normally, the fifo depth and the programm able trigger levels will give the cpu ampl e time to empty the rx fifo before an overrun occurs. one side-effect of having a rx fifo is that the selected inte rrupt trigger level may be above the data level in the fifo. this could occur when data at the end of the block contains fewer bytes than the trigger level. no interrupt would be issued to the cpu and the data would remain in the uart. to prevent the software from having to check for this situation the chip incorporates a timeout interrupt. the timeout interrupt is activated when there is a least one byte in the rx fi fo, and neither the cpu nor the rx shift register has accessed the rx fi fo within 4 character times of the last byte . the timeout interrupt is cleared or reset when the cpu reads the rx fifo or another character enters it.
? 2005 - 2015 microchip technology inc. ds00002020a-page 33 SIO1007 9.7 logical device irq and dma operation any time the irq or dma channel for a uart logical block is disabled by a register bit in that logical block, the irq and/or dma channel is disabled. this is in addition to the irq and dma channel di sabled by the configuration registers (active bit or address not valid). the modem control register (mcr) bit d2 (out2) - when out2 is a logic "0", the serial port interrupts disabled. disabling dma enable bit, disables dma for uart2. refer to the ircc specification. 9.8 output pin states the txd1, nrts1 & ndtr1 pin states change prior to inti alization depending on vcc por, and the state of the uart1 power bit (bit[3] in cr02 on page 61 ). table 9-6: output pin states power cr02 bit[3] vcc por state of txd1, nrts1 & ndtr1 pins 0 default active edge tristate 0 after por tristate 1high
SIO1007 ds00002020a-page 34 ? 2005 - 2015 microchip technology inc. 10.0 infrared interface the SIO1007 contains two infrared (ir) blocks: ircc2.0 and circc2. the ircc2.0 block is an irda v1.2 compliant port and the circc2.0 block is a dedicated consumer ir port. the SIO1007 ircc2.0 block provides a two-way wireless communications port using infrared as the transmission medium. the ircc2.0 block provides t he following protocols: irda v1.2 (s ir/fir), askir, and consumer ir. for detailed description of the ircc2.0 block see ircc 2.x block data sheet (contact microchip, unpublished) the ircc2.0 block implemented in the SIO1007 has a chip id va lue of 0xf2 in sce register, block 3, address 2 and con- tains a gp counter, dual ir support and a 128 byte fifo. the SIO1007 circc2.0 block provides a wireless communicati ons port for receiving and transmitting cir protocols. in particular, it has special logic to re cognize and decode nec ppm and rc5 prot ocols. when the 8051 and the host are both in a sleep state, the cir block can be configured to generate a wake event when it detects a command via one of these protocols. for detailed description of the circc2.0 block see circc 2.x bl ock specification revision 0.7, dated august 26, 2004. 10.1 cir and fir overview 10.1.1 irda sir/fir and askir irda sir (v1.0) specifie s asynchronous serial communication at baud rate s up to 115.2kbps. each byte is sent serially lsb first beginning with a zero value start bit. a zero is signa led by sending a single infrared pulse at the beginning of the serial bit time. a one is signaled by the absence of an infrared pulse during the bit time. please refer to section 20.0, "timing diagrams" for the parameters of these pulses and the irda waveforms. irda fir (v1.2) includes irda v1.0 sir and additionally s pecifies synchronous serial communications at data rates up to 4mbps. data is transferred lsb first in packets that can be up to 2048 bits in length. irda v1.2 includes 576mbps and 1.152mbps data rates using an encoding scheme that is similar to sir. the 4mbps data rate uses a pulse position modulation (ppm) technique. the askir infrared allo ws asynchronous serial communicat ion at baud rates up to 19.2kb ps. each byte is sent serially lsb first beginning with a zero value start bit. a zero is signaled by sending a 500khz carrier waveform for the duration of the serial bit time. a one is signaled by the absence of carrier during the bit time. refer to section 20.0, "timing dia- grams" for the parameters of the askir waveforms. 10.1.2 consumer ir the SIO1007 consumer ir interface is a general-purpose amplitude shift ke yed encoder/decoder with programmable carrier and bit-cell rates that can emulate many popular tv remote encoding formats; including, 38khz ppm, nec ppm and rc5. the carrier frequency is programmable from 1. 6mhz to 6.25khz. the bit-cell rate range is 100khz to 390hz. 10.2 ircc2.0 infrared interface the irda v1.0 (sir) and askir formats are driven by the ace registers fou nd in uart2. the uart2 registers are described in "serial port (uart)" section. the base a ddress for uart2 is programmed in cr25, the uart2 base address register (see cr25 on page 74 ). the irda v1.2 (fir) and consumer ir formats are driven by the sce registers. descriptions of these registers can be found in the infrared communications controller specification. the base address for the sce registers is programmed in cr2b, the sce base address register (see cr2b on page 76 , cr1e on page 71 ). the base address may be pro- grammed when the sce (fir) logical device activate bit in cr3a -bit0 is cleared to 0 and no address decoding takes place for the sce (fir) logical device. 10.2.1 ircc2.0 hardware interface the ircc2.0 ir hardware interface is shown in figure 10-1: on page 36 . this interface supports two types of external fir transceiver modules. one uses a mode pin (ir mode) to program the data rate, while the other has a second rx data pin (irrx3). these functions are selected through cr29 as shown in table 10-1 .
? 2005 - 2015 microchip technology inc. ds00002020a-page 35 SIO1007 note 10-1 hpmode is cr29, bit 4 (see cr29 on page 75 ). refer to figure 10-1, "infrared interface block diagram" for hpmode implementation. the fast bit is used to select between the sir mode and fir mode receiver, regardless of the transceiver type. if fast = 1, the fir mode receiver is selected; if f ast = 0, the sir mode receiver is selected ( ta b l e 1 0 - 2 ). 10.2.2 ir half duplex turnaround delay time if the half duplex option is chosen there is an ir half duplex time-out that constrai ns ircc direction mode changes. this time-out starts as each bit is transferred and prevent s direction mode changes until the time-out expires. the timer is restarted whenever new data arrives in the current direct ion mode. for example, if data is loaded into the transmit buffer while a character is being received, the transmission will not start until the last bit has been received and the time- out expires. if the start bit of another character is received during this time-out, the timer is restarted after the new char- acter is received. the half duplex time-out is programmable from 0 to 25.5ms in 100 s increments (see cr2d on page 77 ). table 10-1: fir transceiver module-type select hp mode ( note 10-1 )function 0ir mode 1 irrx3 table 10-2: ir rx data pin selection control signals inputs fast hpmode rx1 rx2 0 x rx1=rxd2 rx2=irrx2 x 0 rx1=rxd2 rx2=irrx2 1 1 rx1=ir mode/irrx3 rx2=ir mode/irrx3
SIO1007 ds00002020a-page 36 ? 2005 - 2015 microchip technology inc. 10.2.3 ircc2.0 irtx transmit pins the irtx2 pin defaults to output, low on vcc por and pci rese t. this pin is not powered by vtr. this pin functions as described below. following a vcc por, the irtx2 pins will be output and low. they will remain low until one of the following conditions are met. irtx2 pin ( cr0a on page 63 bits [7:6]=01): ? this pin will remain low following a vcc por until serial port 2 is enabled by setting the uart2 power down bit (cr02, bit 7), at which time the pin will reflect the state of the ir transmit output of the ircc block (if ir is enabled through the ir option register for serial port 2). the irtx2 pin will be driven low whenever serial port 2 is disabled (uart2 power down bit is cleared). note that bits[7,6] of cr0a can be used to override this functionality of driving the ir tx2 pin low when uart2 is pow- ered down. if these bit are set to '11', then the irtx2 pin is high-z. 10.2.4 generating ircc 2.0 interrupt events the ircc2.0 block generates one type of interrupt event: a runtime event. the runtime event (if enabled) may be report ed as an smi event or a serial irq event. the description of the ?int? that is us ed to generate a runtime even t from the sce block. the interrupt status and enable bits in the ircc2,0 block are defined in the ircc 2.x block data sheet (contact microchip, unpublished). if a runtime event occurs bit[1] of the smi_sts2 register at offset 09h of the runtime register block will be set. if bit[1] of the smi_en2 register is one and if smi?s are enabled on the io_smi# pin an smi event will be generated. this runtime event can also be routed to the serial irqs. to enable serial irqs for the ircc2.0 runtime events, soft- ware must select an irq channel in the uart interrupt selection register. see cr28 on page 74 . figure 10-1: infrared interface block diagram ircc block raw tv ask irda fir com out mux com ir aux tx1 rx1 tx2 rx2 tx3 rx3 1 2 ir mode fast hpmode 0 1 1 0 g.p. data fast bit irtx2 irrx2 ir mode /irrx3
? 2005 - 2015 microchip technology inc. ds00002020a-page 37 SIO1007 application note: to generate a serial irq for the ircc2.0 block, the ace block must be located in a valid base i/o range and the out2 bit in the mcr register must be set to 1. 10.3 irda pme wakeup the ir receive activity can wake up the system from a sleep state using the SIO1007 nio_pme output. the irrx2 pin wake event is falling edge detected. application note: very narrow pulses, which are rejected by the ircc block, can generate wakeup events. 10.4 circc2 infrared interface the following section describes the featur es that are unique to the circc2 blo ck in the SIO1007. for more information, consult the circc 2.x block specificati on revision 0.7, dated august 26, 2004. 10.4.1 circc2 pin interface the cirrx and cirtx signals that are multiplexed on the gp15 and gp16 pins re spectively are used to interface to the circc2 block. application note: if cirtx signal function is used and interf aced to a transceiver requiring duty cycle protection, an external 5kohm pulldown resistor should be used. in addition the an internal 45a pullup resistor on the cirtx pin should be disabled by clearing the the gp16 bit in cr38 on page 82 . the circc2 block has three ports that can be used to bring out the ir signals to three different pairs of pins. in the SIO1007 implementation, only one of these ports is utilized (see figure 10-2 ). this port is sele cted by the circc2 out- put mux bits, which may be programmed in the cr0a configuration register (see section 18.4.11, "cr0a," on page 63 ) or in the sce configuration register b, which is located in the circc2 runtime registers. the sce configuration reg- ister b is located in register block one of the circc2 runtime registers, which is defined in the circc 2.x block specification revision 0.7, dated august 26, 2004. figure 10-2: circc2 infrare d interface block diagram circc2 block ra w t v ou t mu x co m ir au x tx 1 rx 1 tx 2 rx 2 tx 3 rx 3 n/ a n/ a n/ a n/ a cirtx cirrx
SIO1007 ds00002020a-page 38 ? 2005 - 2015 microchip technology inc. 10.4.2 circc2 operat ional power states the circc2 block is powered by vtr. this block is fully operational under vcc and supports nec ppm and rc5 wake events under vtr only (vcc=0v). when vcc is on, the circc2 clock source is derived from the 14.318mhz clock input. when vcc is off, the circc2 clock source may be derived from the internal pll to prov ide clock support for the cir wake features. the cir wake features are only operational if the clocki32 pin is connected to a 32khz suspend clock, the alternate function on the gp13/irqin1/clki32 pin is conf igured for clocki32, and the clocki32 pll is powered. the clocki32 signal is the alte rnate function on the gp13/irqin1/clki32 pi n. the functions for this pin are selected by the cr34 on page 80 . the clocki32 pll is enabled when vcc transitions to the of f state if the pll is powered. the pll defaults to the off state to conserve power. to enable the pll to operate when the device is in a sleep state (vtr only) the circc2 pll can be enabled via the circc2 pll power bit located in bit[5] of cr02. see cr02 on page 61 . 10.4.3 configuring the circc2 block the circc2 block defaults to the powered down state. to enable the circc2 block to be operational the circc2 log- ical device base address must initialized via cr1f and cr20 , the activate bit in cr3a -bit2 set to one and the circc2 power down bit in cr02 must be set to one. the configuration and control registers for the circc2 block are located in the sce registers defined in the consumer infrared communications controller 2 (circc2) specification. some of these registers are shadowed in the SIO1007 configuration registers. the following table summarizes all th e registers that are shadowed in the configuration register space for the circc2 block. the table lists the configurati on register location, the corresponding sce register location, the read/write ability in both lo cations and the por conditions for each corresponding location. note 10-2 the circc2 half duplex timeout register (shaded in the table below) is reset on a vcc por in config space, which overrides the sce condition to reset on vtr por only note 10-3 the circc2 sce registers are implemented as blocks of registers that are directly addressable at the programmed circc2 base i/o address plus an offset. table 10-3: summary of por and read/w rite conditions for circc2 shadowed registers/bits cr# configuration register/b its sce/ace registers/bits read/write por condition for specific bits cr sce cr sce cr0a ecp fifo threshold/ir mux ? bits[5:4] circc2 output mux sce: register block 1, address 1, ? bits[d7:d6] output mux for circc2 block r/w r/w vtr only vtr only cr0b circc2 mode register ? bits[5:0] sce: register block 1, address 0, ? bits[5:0] are shadowed in register block 1, address 0, bits[d5:d0] r/w r/w vtr only vtr only cr18 circc2 irq/dma select register ? bits[7:4] circc2 irq select ? bits[3:0] circc2 dma select sce: register block 3, address 4, ? bits[7:4] circc2 irq select ? bits[3:0] circc2 dma select r/w read- only vcc - cr19 circc2 software select a sce: register block 3, address 5 r/w read- only vcc - cr1a circc2 software select b sce: register block 3, address 6 r/w read- only vcc - cr1b circc2 half duplex timeout ( note 10-2 ) sce: register block 5, address 1 yes yes vcc vtr only
? 2005 - 2015 microchip technology inc. ds00002020a-page 39 SIO1007 10.4.4 generating circc2 interrupt events the circc2 block generates two types of inte rrupt events: a wake event and a runtime event. the wake event, if enabled, can be used to generate a pme event to wake the system. the circc2 block can be used to generate a wake event for an nec ppm and rc5 event. to generate a wake event, the circc2 block must first be powered and enabled (see circc2 operational power states on page 38 ). the cir mode, nec ppm and rc5, is configured directly in the sce registers. the pme event is r eported in bit[1] of the pme_sts2 register at offset 03h of the runtime register block. this status event can be used to generate a pme interrupt if bit[2] of the pme_en2 register is enabled and pmes are enabled in th e pme_en register at offset 01h. see section 17.0, "runtime registers," on page 53 . the runtime event (if enabled) may be reported as an smi ev ent or a serial irq event. the following diagram shows the interrupt event (int) that is used to generate a runtime ev ent. to have a runtime event, the individual status events must be enabled. in addition to the individual interrupt en ables, the master interrupt en able located in the sce master block control register must also be enabled. these interr upt status and enable bits are defined in the consumer infra- red communications controller 2 (circc2) sp ecification. if a runtime event occurs bit[3] of the smi_sts2 register at offset 09h of the runtime register block will be set. if bit[3] of the smi_en2 regi ster is one and if smi?s are enabled on the io_smi# pin an smi event will be generated. this runtime event can also be routed to the serial irqs. to enable serial irqs for the circc2 runtime events software must select an irq cha nnel in the circc2 irq/dma select register. see cr18 on page 68 .
SIO1007 ds00002020a-page 40 ? 2005 - 2015 microchip technology inc. 11.0 power management power management capabilities are provided for the followi ng logical devices: uart 1, and uart 2. for each logical device, two types of power management are provided: direct powerdown and auto powerdown. 11.1 uart power management direct power management is controlled by cr02. refer to the configuration section for more information. auto power management is enabled by the uart1 and uart 2 enable bits in cr07. when set, these bits allow the following auto power management operations: 1. the transmitter enters auto powerdown when the tr ansmit buffer and shift register are empty. 2. the receiver enters powerdown when t he following conditions are all met: a) receive fifo is empty b) the receiver is waiting for a start bit. 11.1.1 exit auto powerdown the transmitter exits powerdown on a write to the xmit buff er. the receiver exits auto powerdown when rxdx changes state. note: while in powerdown the ring indicator interrupt is st ill valid and transitions when the ri input changes.
? 2005 - 2015 microchip technology inc. ds00002020a-page 41 SIO1007 12.0 serial irq the SIO1007 supp orts the serial interrupt to transmit interrupt in formation to the host system. the serial interrupt scheme adheres to the serial irq spec ification for pci systems, version 6. 0. the pci_clk, ser_irq and nclkrun pins are used for this interface. the serial irq/clkrun enab le bit d7 in cr29 activates the serial interrupt interface. 12.1 timing diagrams for ser_irq cycle a) start frame timing with source sampled a low pulse on irq1 b) stop frame timing with host using 17 ser_irq sampling period note: h=host control; r=recovery; t=turn-a round; sl=slave control; s=sample 1. start frame pulse can be 4-8 clocks wide depending on t he location of the device in the pci bridge hierarchy in a synchronous bridge design. note: h=host control; r=recovery; t= turn-around; s=sample; i=idle 1. stop pulse is 2 clocks wide for quiet mode, 3 clocks wide fo r continuous mode. 2. there may be none, one or more idle states during the stop frame. 3. the next ser_irq cycle?s start frame pulse may or may not start immediately after the turn-around clock of the stop frame.
SIO1007 ds00002020a-page 42 ? 2005 - 2015 microchip technology inc. 12.1.1 ser_irq cycle control there are two modes of operatio n for the ser_irq start frame. 1) quiet (active) mode : any device may initiate a start frame by driving the ser_irq low for one clock, while the ser_irq is idle. after driving low for one clock the ser_irq is immediately tri-stated without at any time driving high. a start frame may not be initiated while the ser_irq is ac tive. the ser_irq is idle between stop and start frames. the ser_irq is active between start and stop frames. this mode of operation allows the ser_irq to be idle when there are no irq/data transitions wh ich should be most of the time. once a start frame has been initiated, the host controller will take over driving the ser_irq low in the next clock and will continue driving the ser_irq low fo r a programmable period of th ree to seven clocks. this makes a total low pulse width of four to eight clocks. finally, the host controller will drive the ser_irq back high for one clock, then tri-state. any ser_irq device (i.e., the SIO1007) which detects any transition on an irq/data line for which it is responsible must initiate a start frame in order to update the host co ntroller unless the ser_irq is already in an ser_irq cycle and the irq/data transition can be delivered in that ser_irq cycle. 2) continuous (idle) mode : only the host controller can initiate a start frame to update irq/data line information. all other ser_irq agents become passive and may not initiate a start frame. ser_irq will be driven low for four to eight clocks by host controller. this mode has two functions. it can be used to stop or idle the ser_irq or the host controller can operate ser_irq in a continuous mode by initiati ng a start frame at the end of every stop frame. an ser_irq mode transition can only occur during the stop fr ame. upon reset, ser_irq bus is defaulted to contin- uous mode, therefore only the host contro ller can initiate the first start frame. slaves must continuously sample the stop frames pulse width to determine the next ser_irq cycle?s mode. 12.1.2 ser_irq data frame once a start frame has been initiated, the SIO1007 will wa tch for the rising edge of the start pulse and start counting irq/data frames from there. each irq/data frame is thr ee clocks: sample phase, reco very phase, and turn-around phase. during the sample phase, the SIO1007 drives the ser_irq low, if and only if, its last detected irq/data value was low. if its detected irq/data value is high, ser_irq is left tri-stated. during the recovery phase, the SIO1007 drives the ser_irq high, if and only if, it had driven the ser_irq low during t he previous sample phase. during the turn-around phase, the SIO1007 tri-states the ser_irq. the SIO1007 will drive the ser_irq line low at the appro- priate sample point if its associated irq/data line is low, regardless of which devic e initiated the start frame. the sample phase for each irq/data follows the low to high transition of the start frame pulse by a number of clocks equal to the irq/data frame times three, minus one. (e.g. the irq5 sample clock is the sixth irq/data frame, (6 x 3) - 1 = 17th clock after the rising edge of the start pulse). table 12-1: ser_irq sampling periods ser_irq period sign al sampled # of clocks past start 1 not used 2 2irq1 5 3 nio_smi/irq2 8 4irq3 11 5irq4 14 6irq5 17 7irq6 20 8irq7 23 9irq8 26 10 irq9 29 11 irq10 32 12 irq11 35 13 irq12 38 14 irq13 41 15 irq14 44 16 irq15 47
? 2005 - 2015 microchip technology inc. ds00002020a-page 43 SIO1007 the ser_irq data frame supports irq2 from a logical devic e on period 3, which can be used for the system manage- ment interrupt (nsmi). when using period 3 for irq2 the user should mask off the smi via the smi enable register. likewise, when using period 3 for nsmi the user shou ld not configure any logical devices as using irq2. ser_irq period 14 is used to transfer irq13. logical devices serial port 1, serial port 2 have irq13 as a choice for their primary interrupt. the smi is enabled onto the smi frame of the serial irq via bit 6 of smi enable register 2 and onto the nio_smi pin via bit 7 of the smi enable register 2. 12.1.3 stop cycle control once all irq/data frames have completed the host cont roller will terminate ser_irq activity by initiating a stop frame. only the host controller can in itiate the stop frame. a stop frame is indicated when the ser_irq is low for two or three clocks. if the stop frame?s low time is two clocks then the next ser_irq cycle?s sampled mode is the quiet mode; and any ser_irq device may initiate a start fram e in the second clock or more after the rising edge of the stop frame?s pulse. if the stop fr ame?s low time is three clocks then th e next ser_irq cycle?s sampled mode is the continuous mode; and only the host controller may initiate a start frame in the second clock or more after the rising edge of the stop frame?s pulse. 12.1.4 latency latency for irq/data updates over the ser_irq bus in bridge-less system s with the minimum host supported irq/data frames of seventeen, will range up to 96 clocks (3.84 ? s with a 25mhz pci bus or 2.88us with a 33mhz pci bus). if one or more pci to pci bridge is added to a system, the latency for irq/data updates from the secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses. 12.1.5 eoi/isr read latency any serialized irq scheme has a potential implementation issue related to irq latency. irq latency could cause an eoi or isr read to precede an irq transit ion that it should have followed. th is could cause a syst em fault. the host interrupt controller is responsible for ensuring that these latency issues are mitigated. the recommended solution is to delay eois and isr reads to the interrupt controller by the same amount as the ser_irq cycle latency in order to ensure that these events do not occur out of order. 12.1.6 ac/dc specification issue all ser_irq agents must drive / sample ser_irq synchrono usly related to the rising edge of pci bus clock. the ser_irq pin uses the electrical specification of pci bus. el ectrical parameters will follow pci spec. section 4, sustained tri-state. 12.1.7 reset and initialization the ser_irq bus uses pci_reset# as its reset signal. the ser_irq pin is tri-stated by all agents while pci_re- set# is active. with reset, ser_irq slaves are put into the (continuous) idle mode. the host controller is responsible for starting the initial ser_irq cycle to collect system?s irq/data default values. the syst em then follows with the con- tinuous/quiet mode protocol (s top frame pulse width) for subsequent ser_irq cycles. it is host controller?s respon- sibility to provide the default values to 8259?s and other syst em logic before the first ser_irq cycle is performed. for ser_irq system suspend, insert ion, or removal application, the host controller should be programmed into continuous (idle) mode first. this is to ensure ser_irq bus is in idle state before the system configuration changes. 12.2 routable irq inputs the routable irq input (irqinx) functions are muxed onto gp13 and gp14 respectively as inputs. the irqinx pin?s irq time slot in the serial irq stream is selected via a 4- bit control register for each ir qin function (cr29 for irqin1, cr2a for irqin2). a value of 0000 disables the irq function. the part is able to generate a pme and an smi from both of the irq inputs through the gpio bits in the pme and smi status and enable registers. the edge is programmable th rough the polarity bit of the gpio control register. user note: in order to use an irq for one of the irqin x inputs that are muxed on the gpio pins, the corresponding irq must not be used for any of the devices in the SIO1007. otherwise contention may occur.
SIO1007 ds00002020a-page 44 ? 2005 - 2015 microchip technology inc. application note: if gpio function is selected on gp13/irqin1/ clki32 and gp14/irqin2 pins and if irq is selected using the routing registers (cr29 fo r irqin1 and cr2a for irqin2), irqs will be generated on the serial irq stream. the state of the gpio pins will be reflected on the serial irq stream. the irq selection bits should be ?0000? in the irq routing registers when gpio functions are used. these irq selecti on bits default to ?0000? on vcc por.
? 2005 - 2015 microchip technology inc. ds00002020a-page 45 SIO1007 13.0 pci clkrun support 13.1 overview the SIO1007 supports the pci nclkrun signal. nclkrun is used to indicate the pci clock status as well as to request that a stopped clock be started. see figure 13-1 for an example of a typica l system implementation using nclkrun. if the SIO1007 sirq_clkrun_en signal is disabled, it will disable the nclkrun support related to ldrq# in addition to disabling the ser_irq and th e nclkrun associated with ser_irq. nclkrun is an open drain output and an input. refer to the pci mobile design guide rev 1.0 for a description of the nclkrun function. 13.2 nclkrun for serial irq the SIO1007 supports the pci clkrun# signal for the serial irqs. if an sio interrupt occurs while the pci clock is stopped, nclkrun is asserted before the seri al interrupt signal is driven active. see using nclkrun section below for more details. 13.3 nclkrun for ldrq# clkrun# support is also provided in the SIO1007 for the l drq# signal. if a device requests dma service while the pci clock is stopped, clkrun# is asserted to restart the pc i clock. this is required to drive the ldrq# signal active. see using nclkrun section for more details. 13.4 using nclkrun if nclkrun is sampled ?high?, the pci clock is stopped or stopping. if nclkrun is sampled ?low?, the pci clock is starting or started (running). if a device in the SIO1007 asse rts or de-asserts an interrupt or asserts a dma request, and nclkrun is sampled ?high?, the SIO1007 requests the restor ation of the clock by asserting the nclkrun signal asyn- chronously ( table 13-1 ). the SIO1007 holds nclkrun low until it detect s two rising edges of the clock. after the sec- ond clock edge, the SIO1007 dis ables the open drain driver ( figure 13-2 ). the SIO1007 will not assert nclkrun under any conditions if sirq_clkrun_en is inactive (?0?). the sirq_- clkrun_en bit is d7 in cr29. the SIO1007 will not assert nclkrun if it is already driv en low by the central resource; i.e., the pci clock gener- ator in figure 13-1 . the SIO1007 will not assert nclkrun unless the line has been deasserted for two successive clocks; i.e., before the clock was stopped ( figure 13-2 ). note 13-1 ?change/assertion? means either-edge change on any internal irqs routed to the sirq block or assertion of an internal dma request by a device in SIO1007. the ?assertion? detection logic runs asynchronously to the pci clock and regardless of the serial irq mode; i.e., ?continuous? or ?quiet?. note 13-2 the nclkrun signal is ?1? for at least two consecutive clocks befo re SIO1007 asserts (?0?) it. table 13-1: SIO1007 nclkrun function sirq_clkrun_en internal interrupts/ dma requests nclkrun action 0 x x none 1 no change x none change/assertion ( note 13- 1 ) 0 none 1 assert nclkrun ( note 13-2 )
SIO1007 ds00002020a-page 46 ? 2005 - 2015 microchip technology inc. note 1: the signal ?any irq change/drq assertion? is the same as ?change/assertion? in table 13-1 . 2: the SIO1007 continually monitors t he state of nclkrun to maintain the pci clock until an active ?any irq change/drq assertion? condition has been transferred to the host in a ser_irq/dma cycle. for example, if ?any irq change/drq assertion? is asserted before nclk run is de-asserted (not shown in figure 13-2 ), the SIO1007 must assert nclkrun as needed until the ser_irq/dma cycle has completed. figure 13-1: nclkrun system implementation example figure 13-2: clock start illustration pci clock generator (central resource) master target sio nclkrun pci_clk pci_clk clkrun# sirq_clkrun_en any irq change/ drq assertion 1,2 clkrun# driven by sio sio stops driving clkrun# 2 clks min.
? 2005 - 2015 microchip technology inc. ds00002020a-page 47 SIO1007 14.0 general purpose i/o the SIO1007 provides a set of flexible input/output cont rol functions to the system designer through the 16 inde- pendently programmable general purpose i/o pins (gpio). the gpio pins can perform basic i/o and many of them can be individually enabled to generate an smi and a pme. 14.1 gpio pins the following pins include gpio functionality as defined in the table below. note 14-1 these pins have input buffers into the wakeup logic that are powered by vtr. 14.2 description each gpio port has a 1-bit data register. gpios are controlle d by gpio control registers located in the configuration section. the data register for each gpio port is represented as a bit in one of the 8-bit gpio data registers, gp1 and gp3. the bits in these registers reflect the value of the asso ciated gpio pin as follows. pin is an input: the bit is the value of the gpio pin. pin is an output: the value written to the bit goes to the gpio pin. the value is latched on reads and writes. although the bits in gp1 and gp3 default to 0x00 at vtr po r, the value read is affected by the gpio pin state. each gpio pin?s state at vcc por is controll ed by the pin?s programmed configuratio n and the external interface (e.g. input driven low by external device.) each gpio pin has program mable configuration bits in cr31-cr39 which control direc- tion, output types, polarity, and internal pull-ups. for example, the gpio internal pull-ups are controlled by cr37 and cr38 and default at vtr por to pull-up enabled (logic ?1?. ) if not reprogrammed any open input will have logic ?1? at vcc por. this will affect the corresponding bit in the gp1 and gp3 runtime register. the gpio data registers are located in the runtime register block; see the runtime registers section. the gpio ports with their alternate functions and configurat ion state register addresses are listed in table 14-2 . table 14-1: gpio pin functionality name power well default on vtr por pme/smi function gp10 vcc ( note 14-1 ) input pme/smi gp11 vcc ( note 14-1 ) input pme/smi gp12/io_smi# vcc ( note 14-1 ) input io_smi#/ pme/smi gp13/irqin1/clki32 vcc ( note 14-1 ) input pme/smi gp14/irqin2 vcc ( note 14-1 ) input pme/smi gp15 / cirrx vcc ( note 14-1 ) input pme/smi gp16 / cirtx vcc ( note 14-1 ) input pme/smi gp17 vcc ( note 14-1 ) input pme/smi gp30 vcc ( note 14-1 ) input pme gp31 vcc ( note 14-1 ) input pme gp32 vcc ( note 14-1 ) input pme gp33 vcc ( note 14-1 ) input pme gp34 vcc ( note 14-1 ) input pme gp35 vcc ( note 14-1 ) input pme gp36 vcc ( note 14-1 ) input pme gp37 vcc ( note 14-1 ) input pme
SIO1007 ds00002020a-page 48 ? 2005 - 2015 microchip technology inc. note 14-2 the gpio data registers are located at the of fset shown from the run time registers block address. 14.3 gpio control each gpio port has an 8-bit control register that controls the behavior of the pin. thes e registers are defined in the configuration section of this specification. each gpio port may be configured as either an input or an output. if the pin is configured as an output, it can be pro- grammed as open-drain or push-pull. inputs and outputs can be configured as non-inverting or inverting. gpio direction registers determine the port direction, gpio polarity registers determine the signal polarity, and gpio output type register determines the output driver type select. the gpio output type regi ster applies all gpios. the gpio direc- tion, polarity and output type registers control the gpio pi n when the pin is configured fo r the gpio function and when the pin is configured for the alternate function for all pins. the basic gpio configuration options are summarized in ta b l e 1 4 - 3 . in addition, each gpio pin has a programmable weak pull-up (45 ? a) to vcc. the pull-up control is independent of gpio direction, buffer type, and alternate function select ion. each gpio pin has a bit in a gpio pullup register, which enables the pin?s pull-up. table 14-2: general purpose i/o port assignments default function alternate function data register data register bit no. register offset (hex) pullup control register control ( note 14-2 ) pullup register bit no. gpio10 gp1 0 0c cr38 0 gpio11 1 1 gpio12 io_smi# 2 2 gpio13 irqin1 3 3 gpio14 irqin2 4 4 gpio15 5 5 gpio16 6 6 gpio17 7 7 gpio 30 gp3 0 0e cr37 0 gpio 31 1 1 gpio 32 2 2 gpio33 3 3 gpio34 4 4 gpio35 5 5 gpio36 6 6 gpio37 7 7 table 14-3: gpio configuration summary selected function direction bit polarity bit description b0 b1 gpio 0 0 pin is a non-inverted output. 0 1 pin is an inverted output. 1 0 pin is a non-inverted input. 1 1 pin is an inverted input.
? 2005 - 2015 microchip technology inc. ds00002020a-page 49 SIO1007 14.4 gpio operation the operation of the gpio ports is illustrated in figure 14-1 . when a gpio port is programmed as an input, reading it th rough the gpio data register la tches either the inverted or non-inverted logic value present at the gpio pin. writing to a gpio port that is programm ed as an input has no effect ( table 14-4 ). when a gpio port is programmed as an output, the logic value or the inverted lo gic value that has been written into the gpio data register is output to the gp io pin. reading from a gp io port that is programm ed as an output returns the last value written to the data register ( ta b l e 1 4 - 4 ). the SIO1007 provides 16 gpios that can directly generate a pme. see the table in the next section. the gpio polarity registers in the configuration section se lect the edge on these gpio pins that will set the associated status bit in the pme_sts1 ? pme_sts3 registers. the def ault is the low-to-high edge. if the corresponding enable bit in the pme_en1 ? pme_en3 registers and the pme_en bit in the pme_en regi ster is set, a pme will be generated. these registers are located in the runtime registers block, which is located at the address contained in th e configuration registers cr30. the pme status bits for the gpios are cleared on a write of ?1?. in addition, the SIO1007 provides 10 gpios that can directly generate an smi. see th e table in the next section. figure 14-1: gpio function illustration note: figure 14-1 is for illustration purposes only and in not in tended to suggest specific implementation details. table 14-4: gpio read/write behavior host operation gpio input port gpio output port read latched value of gpio pin last write to gpio data register write no effect bit placed in gpio data register
SIO1007 ds00002020a-page 50 ? 2005 - 2015 microchip technology inc. 14.5 gpio pme and smi functionality the provides SIO1007 provides 16 gpios t hat can directly generate a pme. see the table in the next section. the gpio polarity registers in the configuration se ction select the edge on these gpio pins that will set the associated status bit in the pme_sts1 ? pme_sts3 registers. the default is the low-to-high edge. if the corresponding enable bit in the pme_en1 ? pme_en3 registers and the pme_en bit in the pm e_en register is set, a pme will be generated. these registers are located in the runtime regi sters block, which is located at the add ress contained in the configuration reg- isters cr30. the pme status bits for t he gpios are cleared on a write of ?1?. in addition, the SIO1007 provides 8 gpios that can directly generate an smi. the following gpios are dedicated wakeup gpios with a status and enable bit in the pme status and enable registers: gp10-gp17 gp30-gp37 this following is the list of pme status and enable registers for their corresponding gpios: pme_sts1 and pme_ en1 for gp10-gp17 pme_sts3 and pme_ en3 for gp30-gp37 the following gpios can directly generate an smi and have a status and enable bit in the smi status and enable reg- isters. gp10-gp17 the following smi status and enable registers for these gpios: smi_sts1 and smi_en1 for gp10-17 the following table summarizes the pme and smi functionality for each gpio. note 14-3 since gp12 can be used to generate an smi and as the io_smi# output , do not enable gp12 to generate an smi (by setting bit 2 of the smi enable register 1) if the io_ smi# function is selected on the gp12 pin. use gp12 to generate an smi even t only if the smi output is enabled on the serial irq stream. table 14-5: pme and smi functionality gpio pme status and enable registers smi status and enable registers output buffer power gp10-gp11 pme_sts1 & pme_ en1 smi_sts1 and smi_en1 vcc gp12 (see note 14-3 ) vcc gp13-gp17 vcc gp30-gp37 pme_sts1 & pme_en1 none vcc
? 2005 - 2015 microchip technology inc. ds00002020a-page 51 SIO1007 15.0 system management interrupt (smi) the SIO1007 implements a ?group? nio_sm i output pin. the system management interrupt is a non-maskable interrupt with the highest priority level used for os transparent power management. the nsmi group interrupt output consists of the enabled interrupts from super i/o device interrupts (serial port 1 and 2) and m any of the gpios pins. the gp12/nio_smi pin, when selected for t he nio_smi function, can be programmed to be active high or active low via bit 2 in the gpio polarity register 1 (cr32). the nio_smi pin func tion defaults to active low. the output buffer type of the pin can be programmed to be open-drain or pus h-pull via gpio output type register (cr39). the interrupts are enabled onto the group nsmi output via the smi enable registers 1 and 2. the nsmi output is then enabled onto the nio_smi output pin via bit[7] in the smi enable regist er 2. the smi output c an also be enabled onto the serial irq stream (irq2) via bit[ 6] in the smi enable register 2. 15.1 smi registers the smi event bits for the gpios events are located in the sm i status and enable registers 1 and 2. the polarity of the edge used to set the status bit and generate an smi is contro lled by the gpio polarity registers located in the config- uration section. for non-inverted polarity (default) the status bit is set on the low-to-high edge. status bits for the gpios are cleared on a write of ?1?. the smi logic for the gpio events is impl emented such that the output of the stat us bit for each event is combined with the corresponding enable bit in order to generate an smi. the smi event bits for the super i/o devices are located in t he smi status and enable register 1 and 2. all of these status bits are cleared at the source; these status bits are not cleared by a write of ?1?. the smi logic for these events is imple- mented such that each event is direct ly combined with the corresponding enable bit in order to generate an smi. see the runtime registers section for the definition of th e smi status and enable registers.
SIO1007 ds00002020a-page 52 ? 2005 - 2015 microchip technology inc. 16.0 pme support the SIO1007 offers support for power management events (pme s), also referred to as syst em control interrupt (sci) events in an acpi system. a power management event is indi cated to the chipset via the assertion of the io_pme# signal. in the SIO1007, the io_pme# is asserted by active transitions on the ring indicator inputs nri1 and nri2, and programmable edges on gpio pins. th e nio_pme pin can be programmed to be active high or active low via bit 5 in the gpio polarity register 2 (cr34). the nio_pme pin function defaults to active low, open-drain output. the output buffer type of the pin can be programmed to be open-drain or push-pull via bit 7 in t he gpio output type register (cr39). this pin is powered by vtr. see the configuration section for description on these registers. pme functionality is controlled by the pme status and enable registers in the runt ime registers block, which is located at the address programmed in register 0x30 in the config uration section. the pme enable bit, pme_en, globally con- trols pme wake-up events. when pme_en is inactive, t he io_pme# signal can not be asserted. when pme_en is asserted, any wake source whose individual pme wake enable register bit is asserted can cause io_pme# to become asserted. the pme status register indicates that an enabled wake sour ce has occurred and if the pme_en bit is set, asserted the io_pme# signal. the pme status bit is asserted by ac tive transitions of pme wake sources. pme_sts will become asserted independent of the state of the global pme enable, pme_en. the following pertains to the pme status bits for each event: ? the output of the status bit for each event is combi ned with the corresponding enable bit to set the pme status bit. ? the status bit for any pending events must be cleared in order to clear the pme_sts bit. status bits are cleared on a write of ?1?. for the gpio events, the polarity of the edge used to set the status bit and generate a pme is controlled by the gpio polarity registers in the config uration section. for non-inverted polarity (def ault) the status bit is set on the low-to-high edge. status bits are cleared on a write of ?1?. in the SIO1007 the io_pme# pin can be programmed to be an open drain, active low, driver. the SIO1007 io_pme# pin is fully isolated from other external devices that might pu ll the io_pme# signal low; i.e. , the io_pme# signal is capa- ble of being driven high externally by another active devi ce or pullup even when the SIO1007 vcc is grounded, provid- ing vtr power is active. 16.1 pme registers the pme registers are run-time registers as follows. these registers are locate d in system i/o space at an offset from runtime registers block, the address programmed at register 0x30 in the configuration section. the following registers are for gpio pme events: ? pme wake status 1 (pme_sts1), pme wake enable 1 (pme_en1) ? pme wake status 2 (pme_sts2), pme wake enable 2 (pme_en2) ? pme wake status 3 (pme_sts3), pme wake enable 3 (pme_en3) see pme register description in the runtime registers section.
? 2005 - 2015 microchip technology inc. ds00002020a-page 53 SIO1007 17.0 runtime registers 17.1 runtime registers block summary the runtime registers are located at t he address programmed in the runtime register block base address configura- tion registers (high and low byte) located in cr30 & cr21 . the part performs 16-bit addr ess qualification on the runtime register base address (bits[15:0] are decoded). the runtim e register block may be located within the range 0x0100- 0xffff on 16-byte boundaries. decodes are disabled if the runtime register base address is located below 0x100. these registers are powered by vtr. note 17-1 reserved bits return 0 on read. 17.2 runtime registers block description table 17-1: runtime register block summary register offset (hex) type pci reset vcc por vtr por register 00 r/w - - 0x00 pme_sts 01 r/w - - 0x00 pme_en 02 r/w - note 17-1 0x00 pme_sts1 03 r/w - - 0x00 pme_sts2 04 r/w - note 17-1 0x00 pme_sts3 05 r/w - - 0x00 pme_en1 06 r/w - - 0x00 pme_en2 07 r/w - - 0x00 pme_en3 08 r/w - note 17-1 0x00 smi_sts1 09 r/w - - 0x00 smi_sts2 0a r/w - - 0x00 smi_en1 0b r/w - - 0x00 smi_en2 0c r/w - note 17-1 0x00 gp1 0d r - - 0x00 reserved 0e r/w - note 17-1 0x00 gp3 0f r - - 0x00 reserved table 17-2: runtime regi sters block description name/default register offset description pme_sts default = 0x00 on vtr por 00 (r/w) bit[0] pme_status = 0 (default) = 1 set when SIO1007 would norma lly assert the io_pme# signal, independent of the stat e of the pme_en bit. bit[7:1] reserved note: pme_status is not affected by vcc por, soft reset or pci reset. writing a ?1? to pme_status will clear it and cause the SIO1007 to stop asserting io_pme#, in enabled. writin g a ?0? to pme_status has no effect. pme_en default = 0x00 on vtr por 01 (r/w) bit[0] pme_en = 0 io_pme# signal assertion is disabled (default) = 1 enables SIO1007 to assert io_pme# signal bit[7:1] reserved pme_en is not affected by vcc por, soft reset or pci reset
SIO1007 ds00002020a-page 54 ? 2005 - 2015 microchip technology inc. pme_sts1 default = 0x00 on vtr por see note 17-2 02 (r/w) pme wake status register 1 this register indicates the state of the individual pme wake sources, independent of the individual source enables or the pme_en bit. if the wake source has asserted a wake event, the associated pme wake status bit will be a ?1?. bit[0] gp10 bit[1] gp11 bit[2] gp12 bit[3] gp13 bit[4] gp14 bit[5] gp15 bit[6] gp16 bit[7] gp17 the pme wake status register is not affected by vcc por, soft reset or pci reset. writing a ?1? to bit[7:0] will clear it. writing a ?0? to any bit in pme wake status register has no effect. pme_sts2 default = 0x00 on vtr por 03 (r/w) pme wake status register 2 this register indicates the state of the individual pme wake sources, independent of the individual source enables or the pme_en bit. if the wake source has asserted a wake event, the associated pme wake status bit will be a ?1?. bit[0] ri1 bit[1] irrx2 bit[2] circc2 bit[7:3] reserved the pme wake status register is not affected by vcc por, soft reset or pci reset. writing a ?1? to bit[7:0] will clear it. writing a ?0? to any bit in pme wake status register has no effect. pme_sts3 default = 0x00 on vtr por see note 17-2 04 (r/w) pme wake status register 3 this register indicates the state of the individual pme wake sources, independent of the individual source enables or the pme_en bit. if the wake source has asserted a wake event, the associated pme wake status bit will be a ?1?. bit[0] gp30 bit[1] gp31 bit[2] gp32 bit[3] gp33 bit[4] gp34 bit[5] gp35 bit[6] gp36 bit[7] gp37 the pme wake status register is not affected by vcc por, soft reset or pci reset. writing a ?1? to bit[7:0] will clear it. writing a ?0? to any bit in pme wake status register has no effect. pme_en1 default = 0x00 on vtr por 05 (r/w) pme wake enable register 1 this register is used to enable indi vidual SIO1007 pme wake sources onto the io_pme# wake bus. when the pme wake enable register bit fo r a wake source is active (?1?), if the source asserts a wake event so that the associated status bit is ?1? and the pme_en bit is ?1?, the source will assert the io_pme# signal. when the pme wake enable register bit for a wake source is inactive (?0?), the pme wake status register will indica te the state of the wake source but will not assert the io_pme# signal. bit[0] gp10 bit[1] gp11 bit[2] gp12 bit[3] gp13 bit[4] gp14 bit[5] gp15 bit[6] gp16 bit[7] gp17 the pme wake enable register is no t affected by vcc por, soft reset or pci reset. table 17-2: runtime registers block description (continued) name/default register offset description
? 2005 - 2015 microchip technology inc. ds00002020a-page 55 SIO1007 pme_en2 default = 0x00 on vtr por 06 (r/w) pme wake enable register 2 this register is used to enable indi vidual SIO1007 pme wake sources onto the io_pme# wake bus. when the pme wake enable register bit fo r a wake source is active (?1?), if the source asserts a wake event so that the associated status bit is ?1? and the pme_en bit is ?1?, the source will assert the io_pme# signal. when the pme wake enable register bit for a wake source is inactive (?0?), the pme wake status register will indica te the state of the wake source but will not assert the io_pme# signal. bit[0] ri1 bit[1] irrx2 bit[2] circc2 bit[7:3] reserved the pme wake enable register is no t affected by vcc por, soft reset or pci reset. pme_en3 default = 0x00 on vtr por 07 (r/w) pme wake enable register 3 this register is used to enable indi vidual SIO1007 pme wake sources onto the io_pme# wake bus. when the pme wake enable register bit fo r a wake source is active (?1?), if the source asserts a wake event so that the associated status bit is ?1? and the pme_en bit is ?1?, the source will assert the io_pme# signal. when the pme wake enable register bit for a wake source is inactive (?0?), the pme wake status register will indica te the state of the wake source but will not assert the io_pme# signal. bit[0] gp30 bit[1] gp31 bit[2] gp32 bit[3] gp33 bit[4] gp34 bit[5] gp35 bit[6] gp36 bit[7] gp37 the pme wake enable register is no t affected by vcc por, soft reset or pci reset. smi_sts1 default = 0x00 on vtr por see note 17-2 08 (r/w) smi status register 1 this register is used to read the status of the smi inputs. the following bits are cleared on a write of ?1?. bit[0] gp10 bit[1] gp11 bit[2] gp12 bit[3] gp13 bit[4] gp14 bit[5] gp15 bit[6] gp16 bit[7] gp17 smi_sts2 0x00 on vtr por 09 (r/w) smi status register 2 this register is used to read the status of the smi inputs. the bits[3:0] must be cleared at their source. bits[5:4] are cleared on a write of ?1?. bit[0] reserved bit[1] u2int bit[2] u1int bit[3] circc2 bit[7:4] reserved table 17-2: runtime registers block description (continued) name/default register offset description
SIO1007 ds00002020a-page 56 ? 2005 - 2015 microchip technology inc. note 17-2 although the bits in this runtime r egister default at vtr po r to ?0?, the value read is affected by the gpio pin state. each gpio pin?s state at vcc por is controlled by the pin?s programmed configuration and the external interface (e.g. input driven low by external device.) each gpio pin has programmable configuration bits in cr31-cr39 which control direction, out put types, polarity, and internal pull-ups. for example, the gpio inter nal pull-ups are controlled by cr37 and cr38 and default at vtr por to pull-up enabl ed (logic ?1?). if not reprogrammed any open input will have logic ?1? at vcc por. this will af fect this runtime register. smi_en1 default = 0x00 on vtr por 0a (r/w) smi enable register 1 this register is used to enable the differ ent interrupt sources onto the internal group nsmi signal. 1=enable 0=disable bit[0] gp10 bit[1] gp11 bit[2] gp12 bit[3] gp13 bit[4] gp14 bit[5] gp15 bit[6] gp16 bit[7] gp17 smi_en2 default = 0x00 on vtr por 0b (r/w) smi enable register 2 this register is used to enable the differ ent interrupt sources onto the internal group nsmi signal, and the internal group nsmi signal onto the nio_smi gpi/o pin or the serial irq stream on irq2. 1=enable 0=disable bit[0] reserved bit[1] en_u2int bit[2] en_u1int bit[3] en_circc2 bit[5:4] reserved bit[6] en_smi_s (enable group nsmi signal onto serial irq2) bit[7] en_smi (enable group ns mi signal onto io_smi# pin) gp1 default = 0x00 on vtr por see note 17-2 0c r/w general purpose i/o data register 1 bit[0]gp10 bit[1]gp11 bit[2]gp12 bit[3]gp13 bit[4]gp14 bit[5]gp15 bit[6]gp16 bit[7]gp17 gp2 default = 0x00 on vtr por 0d r bit[7:0]reserved gp3 default = 0x00 on vtr por see note 17-2 0e r/w general purpose i/o data register 3 bit[0]gp30 bit[1]gp31 bit[2]gp32 bit[3]gp33 bit[4]gp34 bit[5]gp35 bit[6]gp36 bit[7]gp37 gp4 default = 0x00 on vtr por 0f r bit[7:0]reserved note: reserved bits return 0 on read. table 17-2: runtime registers block description (continued) name/default register offset description
? 2005 - 2015 microchip technology inc. ds00002020a-page 57 SIO1007 18.0 configuration the configuration of the si o1007 is programmed through hardware select able configuration access ports that appear when the chip is placed into the confi guration state. the SIO1007 logical device blocks, if enabled, will operate normally in the configuration state. 18.1 configuration access ports the configuration access ports are the config port, the index port, and the data port ( table 18-2 ). the base address of these registers is controlled by the nrts/s ysopt0 and ndts/sysopt1 pins and by the configuration port base address registers cr1 2 and cr13. the configuration base address at power-up is dete rmined by the sysopt strap option. t he sysopt strap option is latched state of the nrts/sysopt0 and ndts/syso pt1 pins at the deas- serting edge of pcirst#. t he nrts/sysopt0 pin determines the lower by te of the base address and the ndts/sys- opt1 pin determines the upper by te of the base address. see table 18-1 default configuration access ports base address decoded from the sysopt strap option. application note: the nrts1/sysopt0 and the ndts1/sysopt1 pins require extern al pullup/pull-down resistors to set the default base i/o address for configuration to 0x002e, 0x004e, 0x162e, or 0x164e. note 18-1 the index and data ports are active only when the SIO1007 is in th e configuration state. note 18-2 the index port is only readabl e in the configuration state. 18.2 configuration state the configuration registers are used to select programmable chip options. the SIO1007 operates in two possible states: the run state and the configurati on state. after power up by default the chip is in the run state. to program the config- uration registers, the configuration st ate must be explicitly enabl ed. programming the config uration registers typically follows this sequence: 1. enter the configuration state, 2. program the config uration register(s), 3. exit the configuration state. 18.2.1 entering the configuration state to enter the configuration state writ e the configuration access key to the config port. the configuration access key is one byte of 55h data. the sio10 07 will automatically activate the configuration access ports following this pro- cedure. table 18-1: default configuration a ccess ports base address decoded from the sysopt strap option sysopt1 sysopt0 default config port/ index port address 0 0 0x002e 0 1 0x004e 1 0 0x162e 1 1 0x164e table 18-2: configuration access ports port name relative address type config port configuration access ports base address + 0 write index port configuration access ports base address + 0 read/write ( note 18-1 , note 18-2 ) data port configuration access ports base address + 1 read/write ( note 18-2 )
SIO1007 ds00002020a-page 58 ? 2005 - 2015 microchip technology inc. 18.2.2 configuration register programming the SIO1007 contains configuration regi sters cr00-cr39. after the SIO1007 enters the configuration state, configura- tion registers can be programmed by first writing the register index number (00 - 39h) to the configuration select reg- ister (csr) through the index port and then writing or read ing the configuration register contents through the data port. configuration register access remains enabled un til the configuration state is explicitly exited. 18.2.3 exiting the configuration state to exit the configuration state, write one byte of aah data to the config po rt. the SIO1007 will automatically deac- tivate the configuration access ports following this procedure, at which point configuration register access cannot occur until the configurat ion state is explicitly re-enabled. 18.2.4 programming example the following is a configuration register programm ing example written in intel 8086 assembly language. ;----------------------------. ; enter configuration state | ;----------------------------' movdx,02eh;sysopt = 0 movax,055h outdx,al ;----------------------------. ; configure register cr0-crx | ;----------------------------' movdx,02eh moval,00h outdx,al ;point to cr0 movdx,02fh moval,3fh outdx,al ;update cr0 ; movdx,02eh moval,01h outdx,al ;point to cr1 movdx,02fh moval,9fh outdx,al ;update cr1 ; ; repeat for all crx registers ; ;-----------------------------. ; exit configuration state | ;-----------------------------' movdx,02eh movax,aah outdx,al 18.2.5 configuration select register (csr) the configuration select register can only be accessed w hen the SIO1007 is in the configuration state. the csr is located at the index port address and must be initialized with configuration register in dex before the register can be accessed using the data port.
? 2005 - 2015 microchip technology inc. ds00002020a-page 59 SIO1007 18.3 configuration registers summary the configuration registers are set to their default values at power up ( table 18-3 ) and are reset as indicated in table 18-3 and the register descriptions that follow. table 18-3: configuration registers summary register index type pci reset ( note 18-3 ) vcc por vtr por register cr00 r - 0x00 valid config cycle cr01 r/w bit[7]=1 - cr lock cr02 r/w bit[7]=0 0x08 - uart and ir power cr03 r - - - reserved cr04 r/w - 0x00 - uart miscellaneous cr05 r - 0x00 - reserved cr06 r - 0x00 - reserved cr07 r/w bit[6:5]=0 0x00 - auto power mgt cr08 r - 0x00 - reserved cr09 r/w - 0x00 - test 4 cr0a r/w bit[7:6]=0 0x00 0x00 ir mux cr0b r - 0x00 - reserved cr0c r/w 0x02 0x02 - uart mode cr0d r - 0x20 - device id cr0e r - revision - revision id cr0f r/w - 0x00 - test 1 cr10 r/w - 0x00 - test 2 cr11 r/w - 0x00 - test 3 cr12 r/w sysopt0=0:0x2e sysopt0=1:0x4e - configuration base address 0 cr13 r/w sysopt1=0:0x00 sysopt1=1:0x16 - configuration base address 1 cr14 r - - - reserved cr15 r - - - uart1 fcr shadow cr16 r - - - uart2 fcr shadow cr17 r - 0x00 - reserved cr18 r/w - 0x00 - circc2 interrupt/dma selection cr19 r/w - 0x00 - circc2 software select a cr1a r/w - 0x00 - circc2 software select b cr1b r/w - 0x03 - circc2 half duplex timeout cr1c r - 0x00 - reserved cr1d r/w - 0x00 - test 5 cr1e r/w - 0x00 - sce (fir) base address - high byte cr1f r/w - 0x00 - circc2 base address register (low byte) cr20 r/w - 0x00 - circc2 base address register (high byte) cr21 r/w - 0x00 - runtime register base address - high byte cr22 r - 0x00 - reserved cr23 r - 0x00 - reserved cr24 r/w - 0x00 - uart1 base address cr25 r/w - 0x00 - uart2 base address cr26 r - 0x00 - reserved
SIO1007 ds00002020a-page 60 ? 2005 - 2015 microchip technology inc. note 18-3 the bits that control the directi on, polarity and output buffer type of each gpio also affect the alternate function on the gpio. 18.4 configuration register detailed description 18.4.1 cr00 cr00 can only be accessed in the configuration stat e and after the csr has been initialized to 00h. cr27 r - 0x00 - reserved cr28 r/w - 0x00 - uart irq select cr29 r/w - 0x80 - irqin1/h pmode/sirq_clkrun_en cr2a r/w - 0x00 - irqin2 cr2b r/w - 0x00 - sce (fir) base address - low byte cr2c r/w - 0x0f - sce (fir) dma select cr2d r/w - 0x03 - ir half duplex timeout cr2e r/w - 0x00 - software select a cr2f r/w - 0x00 - software select b cr30 r/w - 0x00 - runtime register base address - low byte cr31 r/w - - 0x00 gpio direction register 1 cr32 r/w - - 0x00 gpio polarity register 1 cr33 r/w - 0xff- gpio output type register 1 cr34 r/w - - 0x01 alternate function register cr35 r/w - - 0x00 gpio direction register 3 cr36 r/w - - 0x00 gpio polarity register 3 cr37 r/w - - 0xff gpio pullup register 3 cr38 r/w - - 0xff gpio pullup register 1 cr39 r/w - - 0xff gpio output type register 3 cr3a r/w 0x00 logical device activate register cr3b r/w 0x00 lpc docking base address register high byte cr3c r/w 0x00 lpc docking base address register low byte table 18-4: cr00 valid configuration cycle type: r/w default: 0x00 on vcc por bit no. bit name description 6:0 reserved read only. a read returns 0 7valid a high level on this software-controlled bit can be used to indicate that a valid configuration cycle has occurred. t he control software must take care to set this bit at the appropriate times. set to zero after power up. this bit has no effect on any other hardware in the chip. table 18-3: configuration regi sters summary (continued) register index type pci reset ( note 18-3 ) vcc por vtr por register
? 2005 - 2015 microchip technology inc. ds00002020a-page 61 SIO1007 18.4.2 cr01 cr01 can only be accessed in the configuration stat e and after the csr has been initialized to 01h. 18.4.3 cr02 cr02 can only be accessed in the configuration state and after the csr has been initialized to 02h. note 18-4 power control bits disable the respective logical device and associated pins, however the power control bit does not disable the selected address range for the logical device. to disable the host address registers software must clear the activate bits in cr3a , the logical device activate register. devices that are powered down and still activated wil l participate in plug-and-play range checking. 18.4.4 cr03 register cr03 is reserved. the default value of this register after power up is 00h. table 18-5: cr01 cr lock type: r/w default: 0x80 on vcc por; bit[7] = 1 on pci reset bit no. bit name description 6:0 reserved read only. a read returns ?0?. 7 lock crx a high level on this bit enables the reading and writing of cr00 ?cr39 (default). a low level on this bit di sables the reading and writing of cr00 ? cr39. note: once the lock crx bit is set to ?0?, this bit can only be set to ?1? by a pci reset or power-up reset. table 18-6: cr02 uart and ir power type: r/w default: 0x20 on vtr por; 0xx00000vcc por; bit[7] = 0 on pci reset bit no. bit name description 0-2 reserved read only. a read returns ?0?. 3 uart1 power control note 18-4 0= primary serial port are in power down mode. (default) 1= enables normal operation of the primary serial port 4 reserved read only. a read returns ?0?. 5 circc2 pll power down circc pll power (note: this bit is reset on vtr por only) = 0 the 32.768khz clock pll is runn ing and can replace the 14.318mhz clock source for the circc2 wake ev ent. pll selected by internal pwrgood signal. = 1 the 32.768khz clock pll is unpowered (default) 6 circc2 power control note 18-4 0= sce/fir block is in power down mode. (default) 1= enables normal operatio n of the sce/cir block note: this bit is reset on vtr por only. 7 uart2 power control note 18-4 0= secondary serial port including the sce/fir block are in power down mode. (default on vcc por and pci reset) 1=enables normal operation of the secondary serial port, including the sce/fir block.
SIO1007 ds00002020a-page 62 ? 2005 - 2015 microchip technology inc. 18.4.5 cr04 cr04 can only be accessed in the configuration stat e and after the csr has been initialized to 04h. note 18-5 midi support: the musical instrumental digital interface (midi) operates at 31.25kbaud (+/-1%). 18.4.6 cr05 register cr05 is reserved. the default value of this register after power up is 00h. 18.4.7 cr06 register cr06 is reserved. the default value of this register after power up is 00h. 18.4.8 cr07 cr07 can only be accessed in the configuration state and af ter the csr has been initialized to 07h. cr07 controls auto power management. 18.4.9 cr08 register cr08 is reserved. the default value of this register after power up is 00h. table 18-7: cr04 uart miscellaneous type: r/w default: 0x00 on vcc por bit no. bit name description 3:0 read only. a read returns ?0?. 4midi 1 ( note 18-5 ) serial clock select port 1: a low le vel on this bit disables midi support (default). a high level on this bit enables midi support. 5midi 2 ( note 18-5 ) serial clock select port 2: a low le vel on this bit disables midi support (default). a high level on this bit enables midi support. 7:6 read only. a read returns ?0?. table 18-8: cr07 auto power management and boot drive select type: r/w default: 0x00 on vcc por; bits[6:5] = 00 on pci reset bit no. bit name description 4:0 reserved read only. a read returns 0. 5 uart 2 enable this bit controls the auto power down feature of the uart2. the function is: 0 = auto powerdown disabled (default) 1 = auto powerdown enabled this bit is reset to the default state by por or a hardware reset. 6 uart 1 enable this bit controls the auto power down feature of the uart1. the function is: 0 = auto powerdown disabled (default) 1 = auto powerdown enabled this bit is reset to the default state by por or a hardware reset. 7 reserved read only. a read returns 0.
? 2005 - 2015 microchip technology inc. ds00002020a-page 63 SIO1007 18.4.10 cr09 cr09 can only be accessed in the configuration state and af ter the csr has been initialized to 09h. cr09 is a test control register and all bits must be treated as reserved. 18.4.11 cr0a cr0a can only be accessed in the configuration state and afte r the csr has been initialized to 0ah. cr0a bits [5:4] are circc2 output mux bits and are reset to the default state by a vtr por. cr0a bits [7:6] control the ircc2 output mux and are reset to the default state by a vtr por, vcc por and pci reset. note: all test modes are reserved for microchip use. ac tivating test mode registers may produce undesired results. table 18-9: cr09 test 4 type: r/w default: 0x00 on vcc por bit no. bit name description 0 test 24 reserved for microchip use 1 test 25 2 test 26 3 test 27 4 test 28 5 test 29 6 test 30 7 test 31 table 18-10: cr0a ir mux type: r/w default: 0x00 on vtr por; 00xx0000b vcc por; bits[7:6] = 00 on pci reset bit no. bit name description 3:0 reserved read only. a read returns 0. 4,5 circc2 output mux these bits are used to sele ct circc output mux mode. bit5 bit4 mux mode 0 0 default tristate ( note 18-6 ) 0 1 active device to circc2 port. that is, use cirrx, cirtx (pins 23, 24). when circc2 is inactive (power down bit = 0), then cirtx pin is low. 10reserved.( note 18-6 ) 11reserved.( note 18-6 )
SIO1007 ds00002020a-page 64 ? 2005 - 2015 microchip technology inc. note 18-6 the cirtx pin will tristate when this combinati on is selected. outputs inactive: cirtx is high-z, regardless of mode of circc2 and state of circc2 power control bit. 18.4.12 cr0b register cr0b is reserved. the default value of this register after power up is 00h. 18.4.13 cr0c cr0c can only be accessed in the configuration state and after the csr has been initialized to 0ch. cr0c controls the operating mode of the uart. this register is reset to the default state by a por or a hardware reset. 6,7 ircc2 output mux these bits are used to select ircc2 output mux mode. bit7 bit6 mux mode 0 0 active device to com port (default). this port in not connected. when serial port 2 is inactive (power control bit = 0), then the irtx2 pin is low. 0 1 active device to ir port. is the irrx2, irtx2 are selected. when serial port 2 is inactive (power down bit = 0), then irtx2 pin is low. 1 0 reserved. 1 1 outputs inactive: irtx2 is high-z, regardless of mode of uart2 and state of uart2 power control bit. table 18-11: cr0c uart mode type: r/w default: 0x02 on vcc por and pci reset bit no. bit name description 0 uart 2 rcv polarity 0 = rx input active high (default). 1 = rx input active low. 1 uart 2 xmit polarity 0 = tx output active high. 1 = tx output active low (default). 2 uart 2 duplex this bit is used to define the full/half duplex operation of uart 2. 1 = half duplex 0 = full duplex (default) 3, 4, 5 uart 2 mode uart 2 mode 5 4 3 0 0 0 standard com functionality (default) 0 0 1 irda (hpsir) 0 1 0 amplitude shift keyed ir 0 1 1 reserved 1 x x reserved 6 uart 1 speed this bit enables the high speed mode of uart 1. 1 = high speed enabled 0 = standard (default) 7 uart 2 speed this bit enables the high speed mode of uart 2. 1 = high speed enabled 0 = standard (default) table 18-10: cr0a (continued) ir mux type: r/w default: 0x00 on vtr por; 00xx0000b vcc por; bits[7:6] = 00 on pci reset bit no. bit name description
? 2005 - 2015 microchip technology inc. ds00002020a-page 65 SIO1007 18.4.14 cr0d cr0d can only be accessed in the configuration state and afte r the csr has been initialized to 0dh. this register is read only. cr0d contains the SIO1007 device id. the default value of this register after power up is 0x20 on vcc por. 18.4.15 cr0e cr0e can only be accessed in the configuration state and afte r the csr has been initialized to 0eh. this register is read only. cr0e contains the current SIO1007 chip. revision level starting at 00h. 18.4.16 cr0f cr0f can only be accessed in the configuration state and af ter the csr has been initialized to 0fh. cr0f is a test control register and all bits must be treated as reserved. 18.4.17 cr10 cr10 can only be accessed in the configuration state and af ter the csr has been initialized to 10h. cr10 is a test control register and all bits must be treated as reserved. note: all test modes are reserved for microchip use. ac tivating test mode registers may produce undesired results. table 18-12: cr0f test 1 type: r/w default: 0x00 on vcc por bit no. bit name description 0test 0 reserved for microchip use 1test 1 2test 2 3test 3 4test 4 5test 5 6test 6 7test 7 note: all test modes are reserved for microchip use. ac tivating test mode registers may produce undesired results. table 18-13: cr10 test 2 type: r/w default: 0x00 on vcc por bit no. bit name description 0test 8 reserved for microchip use 1test 9 2 test 10 3test 11
SIO1007 ds00002020a-page 66 ? 2005 - 2015 microchip technology inc. 18.4.18 cr11 cr11 can only be accessed in the configuration state and afte r the csr has been initialized to 11h. cr11 is a test con- trol register and all bits mu st be treated as reserved. 18.4.19 cr12 - cr13 cr12 and cr13 are the SIO1007 configur ation ports base address registers ( table 18-15 and table 18-16 ). these registers are used to relocate the conf iguration ports base address beyond the power-up defaults determined by the sysopt[1:0] pin strap options. cr12 contains the configuration ports base address bits a[ 7:0]. cr13 contains the configuration ports base address bits a[15:8]. the configuration ports base address is reloca table on even-byte boundaries; i.e., a0 = ?0?. at power-up the configuration ports base address is determined by the sysopt[1:0 ] pin strap options. to relocate the configuration ports base address after power-up, first writ e the lower address bits of the new base address to cr12 and then write the upper address bits to cr13. 4 test 12 5 test 13 6 test 14 7 test 15 note: all test modes are reserved for microchip use. ac tivating test mode registers may produce undesired results. table 18-14: cr11 test 3 type: r/w default: 0x00 on vcc por bit no. bit name description 0 test 16 reserved for microchip use 1 test 17 2 test 18 3 test 19 4 test 20 5 test 21 6 test 22 7 test 23 note: writing cr13 changes the configuration ports base address. table 18-13: cr10 (continued) test 2 type: r/w default: 0x00 on vcc por bit no. bit name description
? 2005 - 2015 microchip technology inc. ds00002020a-page 67 SIO1007 note 18-7 the configuration ports base address is relocatable on even-byte boundaries; i.e., a0 = ?0?. note 18-8 writing cr13 changes the configuration ports base address. 18.4.20 cr14 register cr14 is reserved. the default value of this register after power up is 00h. table 18-15: cr12 configuration ports base address byte 0 ( note 18-7 ) type: r/w default: 0x2e (sysopt0=0) 0x4e (sysopt0=1) on vcc por and pci reset bit no. bit name description 0 reserved read only. a read returns 0. 1 a1 configuration ports base address byte 0 for decoder. 2a2 3a3 4a4 5a5 6a6 7a7 table 18-16: cr13 configuration ports base address byte 1 ( note 18-8 ) type: r/w default: 0x00 (sysopt1=0) 0x16 (sysopt1=1) on vcc por and pci reset bit no. bit name description 0 a8 configuration ports base address byte 1 for decoder. 1a9 2a10 3a11 4a12 5a13 6a14 7a15
SIO1007 ds00002020a-page 68 ? 2005 - 2015 microchip technology inc. 18.4.21 cr15 cr15 can only be accessed in the configuration state and after the csr has been initialized to 15h. cr15 shadows the bits in the write-only uart1 run-time fcr register. 18.4.22 cr16 cr16 can only be accessed in the configuration state and after the csr has been initialized to 16h. cr16 shadows the bits in the write-only uart2 run-time fcr register. see cr15 for register description. 18.4.23 cr17 register cr17 is reserved. the default value of this register after power up is 00h. 18.4.24 cr18 cr18 can only be accessed in the configuration state and after the csr has been initialized to 18h. cr18 is used to select the irq channel for circc2 and the dma channel for th e circc2 port. any unselected irq output is in tristate. shared irqs are not supported in the SIO1007. table 18-17: cr15 uart1 fcr shadow register type: r default: n/a bit no. bit name description 0 fifo enable setting this bit to a logic "1" enables both the xmit and rcvr fifos 1 rcvr fifo reset setting this bit to a logic "1" clears all bytes in the rcvr fifo and resets its counter logic to 0. this bit is self clearing. 2 xmit fifo reset setting this bit to a logic "1" clears all bytes in the xmit fifo and resets its counter logic to 0. this bit is self-clearing. 3 dma mode select writing to this bit has no effect on the operation of the uart. 4,5 reserved read only. a read returns 0. 6,7 rcvr trigger these bits are used to set t he trigger level for the rcvr fifo interrupt. bit7 bit6 rcvr fifo trigger level (bytes) 001 014 108 1114 table 18-18: cr18 circc2 interrupt/dma selection type: r/w default: 0x00 on vcc por bit no. bit name description 3:0 circc2 dma select these bits are used to select dma for circc2 port. see dma encoding for cr18 (see table 18-20 ). 7:4 circc2 irq select these bits are used to select irq for circc2 port. see irq encoding for cr18 (see table 18-19 ). note: a circc2 irq event will only be generated if an sce event is active and enabled and the circc2 base i/o address is in the active range (i.e., greater than 100h)
? 2005 - 2015 microchip technology inc. ds00002020a-page 69 SIO1007 18.4.25 cr19 cr19 can only be accessed in the configuration state and afte r the csr has been initialized to 19h. cr19 is directly connected to the sce register block th ree, address 0x05 in the circc2 block . table 18-19: irq encoding bits [7:4] irq selected 0000 none 0001 irq_1 0010 irq_2 0011 irq_3 0100 irq_4 0101 irq_5 0110 irq_6 0111 irq_7 1000 irq_8 1001 irq_9 1010 irq_10 1011 irq_11 1100 irq_12 1101 irq_13 1110 irq_14 1111 irq_15 table 18-20: dma selection bits [3:0] dma selected 0000 reserved 0001 dma1 0010 dma2 0011 dma3 0100 reserved .... .... ?. ?. 1110 reserved 1111 none table 18-21: cr19 circc2 software select a type: r/w default: 0x00 on vcc por bit no. bit name description 0-7 software select a these bits are directly connected to sce register block three, address 0x05 in the circc2 block.
SIO1007 ds00002020a-page 70 ? 2005 - 2015 microchip technology inc. 18.4.26 cr1a cr1a can only be accessed in the configuration state and af ter the csr has been initialized to1ah. cr1a is directly connected to sce register block thr ee, address 0x05 in the circc2 block. 18.4.27 cr1b cr1b can only be accessed in the configuration state and afte r the csr has been initialized to 1bh. cr1b is used to set the circc2 half duplex turnaround delay time for the circc2 port. this value is 0 to 25.5msec in 100sec incre- ments. the circc2 block includes an 8 bit ir half duplex time-out register in sce register block 5, address 1 that interacts with configuration register cr1b. these two registers behave like the ot her circc2 legacy controls where either source uniformly updates the value of both registers when eit her register is explicitly wr itten using iow or following a device-level por. circc2 software rese ts do not affect these registers. the ir half duplex time-out is programmable from 0 to 25.5ms in 100 ? s increments, as follows: ir half duplex time-out = (cr1b) x 100 ? s 18.4.28 cr1d cr1d can only be accessed in the configuration state and af ter the csr has been initialized to 09h. cr1d is a test control register and all bits must be treated as reserved. table 18-22: cr1a circc2 software select b type: r/w default: 0x00 on vcc por bit no. bit name description 0-7 software select b these bits are directly co nnected to sce register block three, address 0x06 in the circc2 block. table 18-23: cr1b circc2 half duplex timeout type: r/w default: 0x03 on vcc por bit no. bit name description 0-7 ir half duplex time out these bits are used to set the ir half duplex turnaround delay time for the ir port. this value is 0 to 25.5msec in 100sec increments. note: all test modes are reserved for microchip use. ac tivating test mode registers may produce undesired results.
? 2005 - 2015 microchip technology inc. ds00002020a-page 71 SIO1007 18.4.29 cr1e cr1e can only be accessed in the configuration state and af ter the csr has been initialized to 1eh. cr1e is used to set the sce (fir) base address - high byte adr[15:11]. the sce (fir) logical device base address is initialized usi ng the base address bits located in two configuration regis- ters: cr2b -low byte and cr1e -high byte. the sce base address can be set to 8160 locations on 8-byte boundaries from 0000h - fff8h. the sce (fir) base address bits a[2:0] are decoded as 000b. the sce (fir) bl ock uses full 16-bit addressing decod- ing. an address matching the sce (fir) base address bits a[ 15:3] is decoded using the specific address bits a[2:0] to target registers in sce (fir). when the sce (fir) logical device activate bit in cr3a -bit0 is cleared to 0, no address decoding takes place for the sce (fir) logical device. 18.4.30 cr1f cr1f can only be accessed in the configuration state and af ter the csr has been initialized to 1fh. cr1f is used to select the low byte of the base address (a dr[9:3] bits of circc2 logical device. the circc2 logical device base address is initialized using the base address bits located in two configuration registers: cr1f -low byte and cr20 -high byte. the circc2 base address can be set to 8,192 locations on 8-byte boundaries from 0000h - fff8h. the circc2 base address bits a[2:0] are decoded as 000b. the circc2 block uses full 16-bit addressing decoding. an address matching the circc2 base address bits a[15:3] is decoded using the specific address bits a[2:0] to target registers in circc2. table 18-24: cr1d test 5 type: r/w default: 0x00 on vcc por bit no. bit name description 0 test 32 reserved for microchip use 1 test 33 2 test 34 3 test 35 4 test 36 5 test 37 6 test 38 7 test 39 table 18-25: cr1e sce (fir) base address register - high byte type: r/w default: 0x00 on vcc por bit no. bit name description 0 adr11 fir base address bits for decoder. 1 adr12 2 adr13 3 adr14 4 adr15 5 reserved reads return 0. wr ites have no effect. 6 reserved reads return 0. wr ites have no effect. 7 reserved reads return 0. wr ites have no effect.
SIO1007 ds00002020a-page 72 ? 2005 - 2015 microchip technology inc. when the activate bit in cr3a -bit2 is cleared to 0, no address decoding takes place for the circc2 logical device. to disable circc2 port, set bit[2] of the activate register located at cr3a. 18.4.31 cr20 cr20 can only be accessed in the configuration state and after the csr has been initialized to 20h. cr20 is used to select the high byte of the base address adr[15:10] bits of circc2 logical device. the circc2 logical device base address is initialized using the base address bits located in two configuration registers: cr1f -low byte and cr20 -high byte. the circc2 base address can be set to 8,192 locations on 8-byte boundaries from 0000h - fff8h. the circc2 base address bits a[2:0] are decoded as 000b. the circc2 block uses full 16-bit addressing decoding. an address matching the circc2 base address bits a[15:3] is decoded using the specific address bits a[2:0] to target registers in circc2. when the activate bit in cr3a -bit2 is cleared to 0, no address decoding takes place for the circc2 logical device. to disable circc2 port, set bit[2] of the activate register located at cr3a. 18.4.32 cr21 cr21 can only be accessed in the configuration state and after the csr has been initialized to 21h. cr21 is used to select the high byte of the base address adr[15:1 2] bits of runtime register logical device. runtime register address decoding: address bits a[11:4] are programmable in cr30 . the runtime register base address bits a[3:0] are decoded as 0000b. an address matc hing the runtime register base address bits a[15:4] decodes the specific address bits a[3:0] for the registers in section 17.0, "runtime registers," on page 53 . table 18-26: cr1f circc2 base address register (low byte) type: r/w default: 0x00 on vcc por bit no. bit name description 0 reserved read only. a read returns 0. 1 adr3 circc2 port base address bits[9:3] for decoder. 2 adr4 3 adr5 4 adr6 5 adr7 6 adr8 7 adr9 table 18-27: cr20 circc2 base address register (high byte) type: r/w default: 0x00 on vcc por bit no. bit name description 0 adr10 circc2 port base address bits[15:10] for decoder. 1 adr11 2 adr12 3 adr13 4 adr14 5 adr15 6 reserved read only. a read returns 0. 7 reserved read only. a read returns 0.
? 2005 - 2015 microchip technology inc. ds00002020a-page 73 SIO1007 the runtime register logical device base address is initializ ed using the base address bits located in two configuration registers: cr30 -low byte and cr21 -high byte. the runtime register base address can be set to 4080 locations on 16- byte boundaries from 0000h - fff0h. the runtime register base address bits a[3:0] are decoded as 000 0b. the runtime register block uses full 16-bit addressing decoding. an address matching the runtime regi ster base address bits a[15 :4] is decoded using the spe- cific address bits a[3:0] to target registers in section 17.0 . when the activate bit in cr3a -bit1 is cleared to 0, no address decoding take s place for the runtime register block log- ical device. . 18.4.33 cr22 register cr22 is reserved. the default value of this register after power up is 00h. 18.4.34 cr23 register cr23 is reserved. the default value of this register after power up is 00h. 18.4.35 cr24 cr24 can only be accessed in the configuration state and after the csr has been initialized to 24h. cr24 is used to select the base address of serial port 1 (uart1). the se rial port can be set to 96 locations on 8-byte boundaries from 100h - 3f8h. to disable serial port 1, set adr9 and adr8 to zero. set cr24.0 to 0 when writing the uart1 base address. serial port 1 address decoding: address bits a[15:10] must be ?000000? to access uart1 re gisters. a[2:0] are decoded as xxxb. table 18-28: cr21 runtime register base address register - high byte type: r/w default: 0x00 on vcc por bit no. bit name description 0 adr12 runtime register base address bits for decoder. 1 adr13 2 adr14 3 adr15 4 reserved reads return 0. wr ites have no effect. 5 reserved reads return 0. wr ites have no effect. 6 reserved reads return 0. wr ites have no effect. 7 reserved reads return 0. wr ites have no effect. table 18-29: cr24 uart1 base address register type: r/w default: 0x00 on vcc por bit no. bit name description 0 reserved read only. a read returns 0. 1 adr3 serial port 1 base address bits for decoder. 2 adr4 3 adr5 4 adr6 5 adr7 6 adr8 7 adr9
SIO1007 ds00002020a-page 74 ? 2005 - 2015 microchip technology inc. 18.4.36 cr25 cr25 can only be accessed in the configuration state and after the csr has been initialized to 25h. cr25 is used to select the base address of serial port 2 (uart2). serial port 2 can be set to 96 locations on 8-byte boundaries from 100h - 3f8h. to disable serial port 2, set adr9 and adr8 to zero. set cr25.0 to 0 when writing the uart2 base address. serial port 2 address decoding: address bits a[15:10] must be ?000000? to access uart2 re gisters. a[2:0] are decoded as xxxb. 18.4.37 cr26 register cr26 is reserved. the default value of this register after power up is 00h. 18.4.38 cr27 register cr27 is reserved. the default value of this register after power up is 00h. 18.4.39 cr28 cr28 can only be accessed in the configuration state and after the csr has been initialized to 28h. cr28 is used to select the irq for serial port 1 (bits 7 - 4) and for serial port 2 (bits 3 - 0). the four bit irq encoding field is defined in table 18-32, "irq encoding" . any unselected irq output (registers cr28 - cr2a) is in tristate. shared irqs are not supported in the SIO1007. table 18-30: cr25 uart2 base address register type: r/w default: 0x00 on vcc por bit no. bit name description 0 reserved read only. a read returns 0. 1 adr3 serial port 2 base address bits for decoder. 2 adr4 3 adr5 4 adr6 5 adr7 6 adr8 7 adr9 table 18-31: cr28 uart interrupt selection type: r/w default: 0x00 on vcc por bit no. bit name description 3:0 uart2 irq select these bits are used to select irq for serial port 2. see table 18-32 . 7:4 uart1 irq select these bits are used to select irq for serial port 1. see table 18-32 . table 18-32: irq encoding bits [3:0] or bits [7:4] irq selected 0000 none 0001 irq_1 0010 irq_2 0011 irq_3 0100 irq_4 0101 irq_5
? 2005 - 2015 microchip technology inc. ds00002020a-page 75 SIO1007 18.4.40 cr29 cr29 can only be accessed in the configuration state and afte r the csr has been initialized to 29h. cr29 controls the hpmode bit and is used to select the irq mapping (bits 0 - 3) for the irqin1 pin. the four bit irq encoding field is defined in table 18-32, "irq encoding" . any unselected irq output (registers cr28 - cr2a) is in tristate. shared irqs are not supported in the SIO1007. 0110 irq_6 0111 irq_7 1000 irq_8 1001 irq_9 1010 irq_10 1011 irq_11 1100 irq_12 1101 irq_13 1110 irq_14 1111 irq_15 table 18-33: uart interrupt operation uart1 uart2 irq pins uart1 out2 bit uart1 irq output state uart2 out2 bit uart2 irq output state uart1 pin state uart2 pin state 0z 0z zz 1asserted0z 1z 1 de-asserted 0 z 0 z 0 z 1 asserted z 1 0 z 1 de-asserted z 0 1 asserted 1 asserted 1 1 1 asserted 1 de-asserted 1 0 1 de-asserted 1 asserted 0 1 1 de-asserted 1 de-asserted 0 0 note: it is the responsibility of the soft ware to ensure that two irq?s are not set to the same irq number. potential damage to chip may result. note: z = don?t care. table 18-34: cr29 irqin1/hpmode/sirq_clkrun_en type: r/w default: 0x80 on vcc por bit no. bit name description 0-3 irqin1 selects the irq for irqin1. (see application note in the routable irq inputs section 12.2 .) 4hpmodesee figure 10-1 ? infrared interface block diagram 0 select irmode (default) 1 select irrx3 5-6 reserved not writeable, reads return ?0? 7 sirq_clkrun_en serial irq and clkrun enable bit. 0 = disable 1 = enable (default) table 18-32: irq encoding (continued) bits [3:0] or bits [7:4] irq selected
SIO1007 ds00002020a-page 76 ? 2005 - 2015 microchip technology inc. 18.4.41 cr2a cr2a can only be accessed in the configuration state and af ter the csr has been initialized to 2ah. cr2a is used to select the irq mapping (bits 0 - 3) for the irqin2 pin. the four bit irq encoding field is defined in table 18-32 on page 74 . any unselected irq output (registers cr28 - cr2a) is in tristate. shared irqs are not supported in the SIO1007. 18.4.42 cr2b cr2b can only be accessed in the configuration state and af ter the csr has been initialized to 2bh. cr2b is used to set the sce (fir) base address adr[10:3]. the sce (fir) logical device base address is initialized usi ng the base address bits located in two configuration regis- ters: cr2b -low byte and cr1e -high byte. the sce base address can be set to 8160 locations on 8-byte boundaries from 0000h - fff8h. the sce (fir) base address bits a[2:0] are decoded as 000b. the sce (fir) block uses full 16-bit addressing decod- ing. an address matching the sce (fir) base address bits a[ 15:3] is decoded using the specific address bits a[2:0] to target registers in sce (fir). when the sce (fir) logical device activate bit cr3a -bit0 is cleared to 0, no address decoding takes place for the sce (fir) logical device. table 18-35: cr2a irqin2 type: r/w default: 0x00 on vcc por bit no. bit name description 3:0 irqin2 selects the irq for irqin2. (see application note in the routable irq inputs section 12.2 .) 7:4 reserved read only. a read returns 0. table 18-36: cr2b sce (fir) base address register - low byte type: r/w default: 0x00 on vcc por bit no. bit name description 0 adr3 fir base address bits for decoder. 1 adr4 2 adr5 3 adr6 4 adr7 5 adr8 6 adr9 7 adr10
? 2005 - 2015 microchip technology inc. ds00002020a-page 77 SIO1007 18.4.43 cr2c cr2c can only be accessed in the configuration state and after the csr has been initialized to 2ch. bits d[3:0] of this register are used to select the dma fo r the sce (fir). bits d[7: 4] are reserved. reserved bits cannot be written and return 0 when read. any unselected dma request output (drq) is in tristate. 18.4.44 cr2d cr2d can only be accessed in the configuration state and after the csr has been initialized to 2dh. cr2d is used to set the ir half duplex turnaround delay time for the ir po rt. this value is 0 to 25.5msec in 100sec increments. the ircc v2.0 block includes an 8-bit ir half duplex time-out register in sce register bloc k 5, address 1 that interacts with configuration register cr2 d. these two registers behave like the other ircc legacy controls where either source uniformly updates the value of both registers when either r egister is explicitly written using iow or following a device- level por. ircc software resets do not affect these registers. the ir half duplex time-out is programmable from 0 to 25.5ms in 100 ? s increments, as follows: ir half duplex time-out = (cr2d) x 100 ? s 18.4.45 cr2e cr2e can only be accessed in the configuration state and afte r the csr has been initialized to 2eh. cr2e is directly connected to sce register block three, address 0x05 in the ircc v2.0 block. table 18-37: cr2c sce (fir) dma select register type: r/w default: 0x0f on vcc por bit no. bit name description 3:0 dma select bit3 bit2 bit1 bit0 dma selected 0 0 0 0 reserved 0001dma1 0010dma2 0011dma3 0 1 0 0 reserved . . . . . . . . . . 1 1 1 0 reserved 1111none 7:4 reserved read only. a read returns 0. table 18-38: cr2d ir half duplex timeout type: r/w default: 0x03 on vcc por bit no. bit name description 0-7 ir half duplex time out these bits are used to set the ir half duplex turnaround delay time for the ir port. this value is 0 to 25.5msec in 100sec increments. table 18-39: cr2e software select a type: r/w default: 0x00 on vcc por bit no. bit name description 0-7 software select a these bits are directly c onnected to sce register block three, address 0x05 in the ircc v2.0 block.
SIO1007 ds00002020a-page 78 ? 2005 - 2015 microchip technology inc. 18.4.46 cr2f cr2f can only be accessed in the configuration state and af ter the csr has been initialized to 2fh. cr2f is directly connected to sce register block three, address 0x06 in the ircc v2.0 block. 18.4.47 cr30 cr30 can only be accessed in the configuration state and after the csr has been initialized to 21h. cr30 is used to select the low byte of the base address (adr[11 :4] bits of runtime register logical device. the runtime register logical device base address is initializ ed using the base address bits located in two configuration registers: cr30 -low byte and cr21 -high byte. the runtime register base address can be set to 4080 locations on 16- byte boundaries from 0000h - fff0h. the runtime register base address bits a[3:0] are decoded as 000 0b. the runtime register block uses full 16-bit addressing decoding. an address matching the runtime regi ster base address bits a[15 :4] is decoded using the spe- cific address bits a[3:0] to target registers in section 17.0, "runtime registers," on page 53 . when the activate bit in cr3a -bit1 is cleared to 0, no address decoding ta kes place for the runtime register block log- ical device. table 18-40: cr2f software select b type: r/w default: 0x00 on vcc por bit no. bit name description 0-7 software select b these bits are directly c onnected to sce register block three, address 0x06 in the ircc v2.0 block. table 18-41: cr30 runtime registers block base address-low byte type: r/w default: 0x00 on vcc por bit no. bit name description 0 adr4 the bits in this register are used to program the location of the runtime register block base address. 1 adr5 2 adr6 3 adr7 4 adr8 5 adr9 6 adr10 7 adr11
? 2005 - 2015 microchip technology inc. ds00002020a-page 79 SIO1007 18.4.48 cr31 cr31 can only be accessed in the configuration state and af ter the csr has been initialized to 31h. cr31 is gpio direction register 1 and is used to select the direction of gp10-gp17 pins. 18.4.49 cr32 cr32 can only be accessed in the configuration state and af ter the csr has been initialized to 32h. cr32 is gpio polarity register 1 and is used to select the polarity of gp10-gp17 pins. table 18-42: cr31 gpio direction register 1 type: r/w default: 0x00 on vtr por bit no. bit name description 0 gp10 the bits in this register are used to select the direction of the gp10-gp17 pins. 0=input 1=output 1gp11 2gp12 3gp13 4gp14 5gp15 6gp16 7gp17 table 18-43: cr32 gpio polarity register 1 type: r/w default: 0x00 on vtr por bit no. bit name description 0 gp10 the bits in this register are used to select the polarity of the gp10-gp17 pins. 0=non-inverted 1=inverted 1gp11 2gp12 3gp13 4gp14 5gp15 6gp16 7gp17
SIO1007 ds00002020a-page 80 ? 2005 - 2015 microchip technology inc. 18.4.50 cr33 cr33 can only be accessed in the configuration state and af ter the csr has been initialized to 33h. cr33 is gpio output register and is used to select the output buffer of gp10-gp17. 18.4.51 cr34 cr34 can only be accessed in the config uration state and after the csr has been initialized to 34h. cr34 is alternate function register 1. it is used to sele ct the polarity io_pme pin, and select alternate function on gp13 and gp14 pins. table 18-44: cr33 gpio output type register 1 type: r/w default: 0xff on vtr por bit no. bit name description 0 gp10 the bits in this register are used to select the output buffer type of the gp10-gp17 pins. 0=push-pull 1=open drain 1gp11 2gp12 3gp13 4gp14 5gp15 6gp16 7gp17 table 18-45: cr34 alternate function and io_pme# configuration register type: r/w default: 0x01 on vtr por bit no. bit name description 0 io_pme# buffer select the bits in this register are used to select the output buffer type of the io_pme# pin 0=push-pull 1=open drain (default) 1 io_pme# polarity select this bit is used to select t he polarity of the io_pme# pin. 0=non-inverted 1=inverted note: configuring this pin function with non-inverted polarity will give an active low output signal. the output type can be either open drain or push-pull. (see bit 4). 2 clki32 alternate function select 0= the alternate function is determined by bit[6] of this register (bit[6] is the gp13 alternate function select bit). (default) 1=clki32 3 gp15 alternate function select 0=gpio 1=cirrx 4 gp16 alternate function select 0=gpio 1=cirtx 5 gp12 alternate. function select 0=gpio 1=nio_smi note: selecting the nio_smi function with gp12 configured with non- inverted polarity will give an acti ve low output signal. the output type can be programmed for open drain via cr33.
? 2005 - 2015 microchip technology inc. ds00002020a-page 81 SIO1007 18.4.52 cr35 cr35 can only be accessed in the configuration state and af ter the csr has been initialized to 35h. cr35 is gpio direction register 3 and is used to select the direction of gp30-gp37 pins. 18.4.53 cr36 cr36 can only be accessed in the configuration state and af ter the csr has been initialized to 36h. cr36 is gpio polarity register 3 and is used to select the polarity of gp30-gp37 pins. 6 gp13 alternate function select if bit[2] of this register is 1 then the gp13 pin is configured as the clki32 input and bit[6] has no effect. if bit[2] of this register is 0 then the alternate function enabled on the gp13 pin is determined by the setting of bit[6] as shown. 7 gp14 alternate function select 0=gpio (see application note in the routable irq inputs section 13.2.) 1=irqin2 table 18-46: cr35 gpio direction register 3 type: r/w default: 0x00 on vtr por bit no. bit name description 0 gp30 the bits in this register are used to select the direction of the gp30-gp37 pins. 0=input 1=output 1gp31 2gp32 3gp33 4gp34 5gp35 6gp36 7gp37 table 18-47: cr36 gpio polarity register 3 type: r/w default: 0x00 on vtr por bit no. bit name description 0 gp30 the bits in this register are used to select the polarity of the gp30-gp37 pins. 0=non-inverted 1=inverted 1gp31 2gp32 3gp33 table 18-45: cr34 (continued) alternate function and io_pme# configuration register type: r/w default: 0x01 on vtr por bit no. bit name description bit [2] bit [6] definition 1xclki32 0 0 gpio (default) 0 1 irqin1
SIO1007 ds00002020a-page 82 ? 2005 - 2015 microchip technology inc. 18.4.54 cr37 cr37 can only be accessed in the configuration state and af ter the csr has been initialized to 37h. cr37 is gpio pull- up register 3 and is used to select the weak pull-up (45 ? a) for gp30-gp37 pins. 18.4.55 cr38 cr38 can only be accessed in the configuration state and af ter the csr has been initialized to 38h. cr38 is gpio pull- up register 1 and is used to select the weak pull-up (45 ? a) for gp10-gp17 pins. 4gp34 5gp35 6gp36 7gp37 table 18-48: cr37 gpio pullup register 3 type: r/w default: 0xff on vtr por bit no. bit name description 0 gp30 the bits in this register are used to select the pull-up of the gp30-gp37 pins. 0=no pull-up 1=pull-up enabled 1gp31 2gp32 3gp33 4gp34 5gp35 6gp36 7gp37 table 18-49: cr38 gpio pullup register 1 type: r/w default: 0xff on vtr por bit no. bit name description 0 gp10 the bits in this register are used to select the pull-up of the gp10-gp17 pins. 0=no pull-up 1=pull-up enabled 1gp11 2gp12 3gp13 4gp14 table 18-47: cr36 (continued) gpio polarity register 3 type: r/w default: 0x00 on vtr por bit no. bit name description
? 2005 - 2015 microchip technology inc. ds00002020a-page 83 SIO1007 18.4.56 cr39 cr39 can only be accessed in the configuration state and af ter the csr has been initialized to 39h. cr39 is gpio output register and is used to se lect the output buffer of gp30-gp37pins. 18.4.57 cr3a cr3a can only be accessed in the configuration st ate and after the csr has been initialized to 3ah. 5gp15 6gp16 7gp17 table 18-50: cr39 gpio output register 3 type: r/w default: 0xff on vtr por bit no. bit name description 0 gp30 the bits in this register are used to select the output buffer type of the gp30-gp37 pins. 0=push-pull 1=open drain 1gp31 2gp32 3gp33 4gp34 5gp35 6gp36 7gp37 table 18-51: cr3a logical device activate register type: r/w default: 0x00 on vcc por bit no. bit name description 0 sce(fir) 0 = disables the host access to sce (fir) logical device (default). 1 = enables the host access to sce (f ir) logical device?s i/o runtime register space for the ircc2.0 block. the i/o address is selected by the sce(fir) base a ddress registers. 1 runtime register 0 = disables the host access to runtime register logical device (default). 1 = enables the host access to runtime register logical device?s i/o register space for the runtime register block. the i/o address is selected by the runtime register base address registers. 2 circc2 0 = disables the host access to circc2 logical device (default). 1 = enables the host a ccess to circc2 logica l device?s i/o runtime register space for the circc2 block. the i/o address is selected by the circc2 base address registers. table 18-49: cr38 (continued) gpio pullup register 1 type: r/w default: 0xff on vtr por bit no. bit name description
SIO1007 ds00002020a-page 84 ? 2005 - 2015 microchip technology inc. note 18-9 the activate bit disables the selected address rang e for the logical device. when the activate bit is set and the corresponding logical device resides at a valid i/o base address, the logical device will participate in plug-and-play range checking. application note: when the activate bit (cr3a bit 3 to ?1?), the values in cr3b and cr3c must be valid; otherwise, an undefined state an d undesired behavior may result. 18.4.58 cr3b-3c cr3b can only be accessed in the configuration state and after the csr has been initialized to 3bh. cr3c can only be accessed in the configuration state and after the csr has been initialized to 3ch. cr3b and cr3c are used to select the base address of lpc docking. valid addresses for lpc docking runtime register space can be set to locations on single -byte boundaries from 0000h - ffffh. to disable lp c docking runtime register dec oding, set the activate bit ( cr3a -bit 3 to ?0?). set cr3a -bit 3 to ?0? (to disable lpc docking runtime register decoding) when writing the lpc docking base address registers cr3b and cr3c. the lpc docking runtime register uses full 16-bit addressing decoding. 3lpc dock note 18-9 a high level on this bit, enables the host access to lpc docking logical device?s i/o runtime register space. the i/o address is selected by the lpc docking base addre ss registers. a low level on this bit disables the host access to lpc docking logical device (default). 4,5,6, 7 reserved read only. a read returns 0 table 18-52: cr3b lpc docking base address register high byte type: r/w default: 0x00 on vcc por bit no. bit name description 0 adr8 lpc docking base address bits for decoder. 1 adr9 2 adr10 3 adr11 4 adr12 5 adr13 6 adr14 7 adr15 table 18-51: cr3a (continued) logical device activate register type: r/w default: 0x00 on vcc por bit no. bit name description
? 2005 - 2015 microchip technology inc. ds00002020a-page 85 SIO1007 18.5 logical device base i/o address and range table 18-53: cr3c lpc docking base address register low byte type: r/w default: 0x00 on vcc por bit no. bit name description 0 adr0 lpc docking base address bits for decoder. 1 adr1 2 adr2 3 adr3 4 adr4 5 adr5 6 adr6 7 adr7 table 18-54: i/o base address config uration register description logical device register index base i/o range fixed base ofsets serial port 1 cr24 see note 18-11 [0x0100:0x03f8] on 8 byte boundaries +0 : rb/tb/lsb div +1 : ier/msb div +2 : iir/fcr +3 : lcr +4 : mcr +5 : lsr +6 : msr +7 : scr serial port 2 (async. comm engine) cr25 see note 18-11 [0x0100:0x03f8] on 8-byte boundaries +0 : rb/tb/lsb div +1 : ier/msb div +2 : iir/fcr +3 : lcr +4 : mcr +5 : lsr +6 : msr +7 : scr serial port 2 (sync. comm engine) cr2b , cr1e (fir/cir) see note 18-9 on page 84 and note 18-11 [0x0000:0x07f8] on 8-byte boundaries +0 : dr/scea/circ/idh/(irdacr/bofh) +1 : intid/sceb/circr/idl/bofl +2 : ier/fifot/cirbr/cid/bwcl +3 : lsr/lsa/vern/(bwch/tdsh) +4 : lca/(irql/dmac)/tdsl +5 : lcb/rdsh +6 : bs/rdsl +7 : mcr circc2 cr1f , cr20 see note 18-9 on page 84 and note 18-11 [0x0000:0x07f8] on 8-byte boundaries +0 : dr/scea/circ/idh/(irdacr/bofh) +1 : intid/sceb/circr/idl/bofl +2 : ier/fifot/cirbr/cid/bwcl +3 : lsr/lsa/vern/(bwch/tdsh) +4 : lca/(irql/dmac)/tdsl +5 : lcb/rdsh +6 : bs/rdsl +7 : mcr runtime register block cr30 , cr21 see note 18-9 on page 84 [0x0000:0x0ff0] on 16-byte boundaries +00 : pme_sts +0f : gp4 (see table 17-1 in the runtime registers section for full list)
SIO1007 ds00002020a-page 86 ? 2005 - 2015 microchip technology inc. note 18-10 the configuration port is at either 0x002e , 0x004e, 0x162e or 0x164e (controlled by the sysopt[1:0] strap options) at power up and can be re located via cr12 and cr13. note 18-11 the uart and ir power register at cr02 power control bits disable the respective logical device and associated pins, however the power control bit does not disable the selected address range for the logical device. to di sable the host address registers software must clear the activate bits in cr3a , the logical device activate re gister. devices that are powered down and still activated will participate in plug-and-play range checking. config. port cr12 - cr13 see note 18-10 [0x0000:0x07fe] on 2-byte boundaries see configuration registers in table 18- 3 . they are accessed through the index and data ports located at the configuration port address and the configuration port address +1 respectively. lpc docking cr3b-3c see note 18-9 on page 84 [0x0000:0x0fff] on single byte boundaries +0 : docking lpc switch register table 18-54: i/o base address configuration re gister description (continued) logical device register index base i/o range fixed base ofsets
? 2005 - 2015 microchip technology inc. ds00002020a-page 87 SIO1007 19.0 operational description 19.1 maximum ratings operating temperature range .................................................................................................... ................0 o c to +70 o c storage temperature range ...................................................................................................... ............... -55 o to +150 o c lead temperature range .......................................... ................................................. refer to jedec spec. j-std-020 positive voltage on any pin, with respect to ground.. .......................................................................... ............. v cc +0.3v negative voltage on any pin, with respect to ground ............................................................................ ...................-0.3v maximum v cc ............................................................................................................................... ...........................+5.5v 19.2 dc electrical characteristics (t a = 0 0 c ? 70 0 c, v cc = +3.3 v 10%) note: ? stresses above those listed above could cause permanent dam age to the device. this is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. ? when powering this device from labora tory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when the ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exists, it is suggested that a clamp circuit be used. parameter symbol min typ max units comments i type input buffer low input level high input level v ili v ihi 2.0 0.8 v v ttl levels is type input buffer low input level high input level schmitt trigger hysteresis v ilis v ihis v hys 2.2 100 0.8 v v mv schmitt trigger schmitt trigger input leakage, i and is buffers low input leakage high input leakage i il i ih -10 -10 +10 +10 a a v in = 0 v in = v cc o6 type buffer low output level high output level v ol v oh 2.4 0.4 v v i ol = 6ma i oh = -3ma io8 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 8ma i oh = -4ma v in = 0 to v cc ( note 19-1 )
SIO1007 ds00002020a-page 88 ? 2005 - 2015 microchip technology inc. o8 type buffer low output level high output level v ol v oh 2.4 0.4 v v i ol = 8ma i oh = -4ma o12 type buffer low output level high output level v ol v oh 2.4 0.4 v v i ol = 12ma i oh = -6ma io12 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 12ma i oh = -6ma v in = 0 to v cc ( note 19-1 ) od12 type buffer low output level output leakage v ol i ol -10 0.4 +10 v a i ol = 12ma v in = 0 to v cc od14 type buffer low output level output leakage v ol i ol -10 0.4 +10 v a i ol = 14ma v in = 0 to v cc op14 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 14ma i oh = -14ma v in = 0 to v cc ( note 19-1 ) iop14 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a i ol = 14ma i oh = -14ma v in = 0 to v cc ( note 19-1 ) progammable pullup current i pu 18 34.5 60 a ( note 19-7 ) backdrive protect/chiprotect ( note 19-5 ) i il 10 a v cc = 0v v in = 5.5v max 5v tolerant pins ( note 19-5 )i il 10 a v cc = 3.3v v in = 5.5v max lpc bus pins ( note 19-5 and note 19-6 ) i il 10 a v cc = 0v and v cc = 3.3v v in = 3.6v max vcc supply current active i cc 10 ( note 19 -2 ) ma all outputs open, all inputs transitioning from/to 0v to/from 3.3v parameter symbol min typ max units comments
? 2005 - 2015 microchip technology inc. ds00002020a-page 89 SIO1007 note 19-1 all output leakage?s are measured with all pins in high impedance note 19-2 these values are estimated. they will be updated after characterization. contact microchip for the latest values. note 19-3 max i tr with v cc = 3.3v (nominal) is 0.2ma. max i tr with v cc = 0v (nominal) is 60a. note 19-4 the minimum value given for v tr applies when v cc is active. when v cc is 0v, the minimum v tr is 0v. note 19-5 see section 5.1, "3.3 volt operation / 5 volt tolerance" . note 19-6 ta b l e 4 - 1 and the associated note 4-5 identify the non-5v tolerant pins. note 19-7 programmable pullup resistance on gpio are controlled by cr37 and cr38. capacitance t a = 25 0 c; fc = 1mhz; v cc = 3.3v 10% trickle supply voltage ( note 19-4 ) v tr v cc min -.5v v cc max v v cc must not be greater than .5v above v tr vtr supply current active ( note 19-2 and note 19-3 ) i tr 7 ma all outputs open, all inputs transitioning from/to 0v to/from 3.3v parameter symbol limits unit test condition min typ max clock input capacitance c in 20 pf all pins except pin under test tied to ac ground input capacitance c in 10 pf output capacitance c out 20 pf parameter symbol min typ max units comments
SIO1007 ds00002020a-page 90 ? 2005 - 2015 microchip technology inc. 20.0 timing diagrams for the timing diagrams shown, the followin g capacitive loads are used on outputs. note 20-1 internal write-protection period after vcc passes 2.7 volts on power-up. name capacitance total (pf) ser_irq 50 nlad[3:0] 50 nldrq 50 txd1 50 nclkrun 50 figure 20-1: power-up timing name description min typ max units t1 vcc slew from 2.7v to 0v 300 s t2 vcc slew from 0v to 2.7v 100 s t3 all host accesses after powerup ( note 20-1 )125 500s figure 20-2: input clock timing name description min typ max units t1 clock cycle time for 14.318mhz 69.84 ns t2 clock high time/low time for 14.318mhz 20 35 ns clock rise time/fall time (not shown) 5 ns t3 vcc all host a ccesses t2 t1
? 2005 - 2015 microchip technology inc. ds00002020a-page 91 SIO1007 figure 20-3: pci clock timing name description min typ max units t1 period 30 33.3 nsec t2 high time 12 nsec t3 low time 12 nsec t4 rise time 3 nsec t5 fall time 3 nsec figure 20-4: reset timing name description min typ max units t1 pci_reset# width 1 ms
SIO1007 ds00002020a-page 92 ? 2005 - 2015 microchip technology inc. figure 20-5: output timing meas urement conditions, lpc signals name description min typ max units t1 clk to signal valid delay ? bused signals 2 11 ns t2 float to active delay 2 11 ns t3 active to float delay 28 ns figure 20-6: input timing measurement conditions, lpc signals name description min typ max units t1 input set up time to clk ? bused signals 7 ns t2 input hold time from clk 0 ns
? 2005 - 2015 microchip technology inc. ds00002020a-page 93 SIO1007 figure 20-7: i/o write note: l1=start; l2=cyctyp+dir; l3=sync of 0000 figure 20-8: i/o read note: l1=start; l2=cyctyp+dir; l3=sync of 0000 figure 20-9: dma request assertion through ldrq#
SIO1007 ds00002020a-page 94 ? 2005 - 2015 microchip technology inc. figure 20-10: dma write (first byte) note: l1=sync of 0000 figure 20-11: dma read (first byte) note: l1=sync of 0000
? 2005 - 2015 microchip technology inc. ds00002020a-page 95 SIO1007 figure 20-12: irda recieve timing t1 t2 t2 t1 01010 011011 data irrx n irrx t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 pa rame ter min ty p m ax units 1. 4 1. 4 1. 4 1. 4 1. 4 1. 4 1. 4 2. 71 3. 69 5. 53 11.07 22.13 44.27 88.55 s s s s s s s s s s s s s s pulse w idt h at 1 15kba ud pul se wid th at 57. 6kba ud pul se wid th at 38. 4kba ud pul se wid th at 19. 2kba ud pu lse wi dt h a t 9. 6kba ud pu lse wi dt h a t 4. 8kba ud pu lse wi dt h a t 2. 4kba ud bit t ime at 1 15kba ud bit t ime at 57. 6kba ud bit t ime at 38. 4kba ud bit t ime at 19. 2kba ud bi t ti me a t 9. 6kba ud bi t ti me a t 4. 8kba ud bi t ti me a t 2. 4kba ud 1. 6 3. 22 4. 8 9. 7 19. 5 39 78 8. 68 17. 4 26 52 104 208 416 no te s: 1. recei ve pu lse det ect ion c ri te ria: a re ceived p ulse is consi dered d et ecte d if t he receive d p ulse is a mini mum o f 1. 41 s. 2. ir rx: l5, crf1 bit 0 = 1 ni rrx: l5, crf 1 bi t 0 = 0 ( def aul t )
SIO1007 ds00002020a-page 96 ? 2005 - 2015 microchip technology inc. figure 20-13: irda transmit timing t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 parameter mi n 1.41 1.41 1.41 1.41 1.41 1.41 1.41 ma x 2.71 3.69 5.53 11.07 22.13 44.27 88.55 units s s s s s s s s s s s s s s pulse width at 115kbaud pulse width at 57.6kbaud pulse width at 38.4kbaud pulse width at 19.2kbaud pulse width at 9.6kbaud pulse width at 4.8kbaud pulse width at 2.4kbaud bit t ime at 115kbaud bit tim e at 57. 6kbaud bit tim e at 38. 4kbaud bit tim e at 19. 2kbaud bit tim e at 9. 6kbaud bit tim e at 4. 8kbaud bit tim e at 2. 4kbaud typ 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 104 208 416 t1 t2 t2 t1 0 1010 011 0 11 dat a irtx n i rt x notes: 1. irda @ 115k i s hpsir compati ble. irda @ 2400 wi ll al low compatib ilit y wit h hp 95lx and 48sx. 2. irt x: l5, crf 1 bit 1 = 1 (default) ni rt x: l5, crf1 bit 1 = 0
? 2005 - 2015 microchip technology inc. ds00002020a-page 97 SIO1007 figure 20-14: amplitude shif t keyed ir receive timing t1 t2 t3 t4 t5 t6 pa rameter min typ max units 0.8 0.8 0.8 0.8 1.2 1.2 1.2 1.2 s s s s s s m odu l ated out put b i t t i me off bit t ime m odu l ated outp ut " on" m odu l ated out put " off" m odu l ated outp ut " on" m odu l ated out put " off" 1 1 1 1 note s: 1 . irrx: l 5, crf 1 bit 0 = 1 n irrx : l5 , crf 1 b i t 0 = 0 (de faul t) m irrx, nmi rrx are the mod ulate d ou tpu ts t1 t2 t3 t4 t5 t6 01010011011 dat a irrx n irrx mirrx nm irrx
SIO1007 ds00002020a-page 98 ? 2005 - 2015 microchip technology inc. figure 20-15: amplitude shif t keyed ir transmit timing figure 20-16: setup and hold time name description min typ max units t1 ser_irq setup time to pci_clk rising 7 nsec t2 ser_irq hold time to pci_clk rising 0 nsec t1 t2 t3 t4 t5 t6 pa ramet er min typ max units 0.8 0.8 0.8 0.8 1.2 1.2 1.2 1.2 s s s s s s m odu lated out put bit t ime off bit t ime m odu lated outp ut " on" m odu lated outp ut " off" m odu lated outp ut " on" m odu lated outp ut " off" 1 1 1 1 note s: 1 . irt x: l5 , crf 1 bit 1 = 1 (def ault) ni rtx: l 5, crf 1 bit 1 = 0 mirt x, nm irt x a re the mod ulate d ou tpu ts t1 t2 t3 t4 t5 t6 01010 011011 dat a irt x n irt x mir t x nmirtx
? 2005 - 2015 microchip technology inc. ds00002020a-page 99 SIO1007 note 20-2 t br is 1/baud rate. the baud rate is programmed through the divisor latch registers. baud rates have percentage errors indicated in the ?baud rate? table in the ?serial port? section. figure 20-17: serial port data name description min typ max units t1 serial port data bit time t br ( note 2 0-2 ) nsec
SIO1007 ds00002020a-page 100 ? 2005 - 2015 microchip technology inc. 21.0 xnor-chain test mode the SIO1007 provides board test capability through the im plementation of xnor chain. see following sub-sections. xnor-chain test structure allows users to confirm that al l pins are in contact with the motherboard during assembly and test operations. see figure 21-1 below. when the chip is in the xnor chai n test mode, setting the state of any of the input pins to the opposite of its current state will cause the output of the chain to toggle. the xnor-chain test structure must be activated to perf orm these tests. when the xnor-chain is activated, the SIO1007 pin functions are disconnected fr om the device pins, which all become i nput pins except for one output pin at the end of xnor-chain. the tests that are performed when the xnor-chain test struct ure is activated require the board-level test hardware to control the device pins and observe the results at the xnor-chain output pin. 21.1 entering and exiting test mode xnor-chain test mode can be entered as follows: on the rising (deasserting) edge of npci_r eset, drive nlframe low and drive lad[0] low. exit xnor-chain test mode as follows: on the rising (deasserting) edge of npci_r eset, drive either nlframe or lad[0] high. the npci_reset pin is not included in the xnor-chain. the xnor-chain output is on the nio_pme pin. see the following subsections for more details. 21.2 pin list of xnor chain all pins on the chip are inputs to the first xnor chain, with the exception of the following: 1. vcc (5 pins) and vtr (1 pin). 2. vss (6 pins). 3. npci_reset 4. nio_pme this is the chain output. to put the chip in the first xnor chain test mode, tie lad0 and nlframe low. then toggle npci_reset from a low to a high state. once the chip is put into xnor chain test mode, lad0 and nlframe become part of the chain. to exit the first xnor chain test mode tie lad0 or nlframe high. then to ggle npci_reset from a low to a high state. a vcc por will also cause the xnor chain test mode to be exited. to verify the test mode has been exited, observe the output at nio_pme. toggling any of the input pins in the chain should not cause its state to change. figure 21-1: xnor-chain test structure i/o#1 i/o#2 i/o#3 i/o#n xnor out
? 2005 - 2015 microchip technology inc. ds00002020a-page 101 SIO1007 21.3 setup of xnor chain warning: ensure power supply is off during setup. 1. connect vss pins to ground. 2. connect vcc pins and vtr pin to vcc (3.3v). 3. connect an oscilloscope, voltmeter, or other measurement device to the nio_pme pin. 4. all other pins should be tied to ground. 21.4 testing procedure 1. turn power on. 2. with lad0 pin and nlframe pin, low, bring npci_reset pin high. the chip is now in xnor chain test mode. at this point, all inputs to the first xnor chain are lo w. the output, on nio_pme (p in 17), should also be low. refer to initial config on table 21-1 . 3. bring pin 64 high. the output on the nio_pme pin should go high. refer to step one on table 21-1 . 4. in descending pin order, bring each input high. the output should switch states each time an input is toggled. continue until all inputs are high. the output on nio_pme should now be low. refer to end config on table 21-1 . 5. the current state of t he chip is now represented by initial config in table 21-2 . 6. each input should now be brought low, starting at pin one and continuing in ascending order. continue until all inputs are low. the nio_pme output should now be low. refer to ta b l e 2 1 - 2 . 7. to exit test mode, tie la d0 (pin 20) or nlframe (p in 24) high, and toggle npci_reset fr om a low to a high state.an odd number of inputs (all grounded) yield a logic hi gh on the chain output pin. if all the inputs are held high the value on the chain output should be low.
SIO1007 ds00002020a-page 102 ? 2005 - 2015 microchip technology inc. table 21-1: toggling inputs in descending order pin 64 pin 63 pin 62 pin 61 pin 60 pin ... pin 1 output pin nio_pme initial configlllll l l l step 1 hllll l l h step 2 h h l l l l l l step 3 h h h l l l l h step 4 hhhhl l l l step 5 hhhhh l l h ? ????? ? ? ? step n-1 hhhhh h l h end config hhhhh h h l table 21-2: toggling inputs in ascending order pin 1 pin 2 pin 3 pin 4 pin 5 pin ... pin 64 output pin nio_pme initial config h h h h h h h l step 1 l h h h h h h h step 2 l l h h h h h l step 3 l l l h h h h h step 4 l l l l h h h l step 5 l l l l l h h h ?????? ? ? step n-1 l l l l l l h h end config l l l l l l l l
? 2005 - 2015 microchip technology inc. ds00002020a-page 103 SIO1007 22.0 package outline note 1: controlling unit: millimeter. 2: tolerance on the true position of the leads is 0.035 mm maximum. 3: package body dimensions d1 and e1 do not include the mold protrusion. 4: maximum mold protrusion is 0.25 mm per side. d1 and e1 dimensions determined at datum plane h. 5: dimension for foot length l measured at th e gauge plane 0.25 mm above the seating plane. 6: details of pin 1 identifier are optional but must be located within the zone indicated. note: for the most current package drawings, see the microchip packaging specification at http://www.microchip.com/packaging . figure 22-1: 64-pin stqfp package min nominal max remarks a ~ ~ 1.60 overall package height a1 0.05 ~ 0.15 standoff a2 1.35 1.40 1.45 body thickness d 8.80 9.00 9.20 x span d1 6.80 7.00 7.20 x body size e 8.80 9.00 9.20 y span e1 6.80 7.00 7.20 y body size h 0.09 ~ 0.20 lead frame thickness l 0.45 0.60 0.75 le ad foot length l1 ~ 1.00 ref. ~ lead length e 0.40 basic lead pitch ? 0 o ~7 o lead foot angle w 0.13 0.18 0.23 lead width ccc ~ ~ 0.08 coplanarity
SIO1007 ds00002020a-page 104 ? 2005 - 2015 microchip technology inc. appendix a: data sheet revision history table a-1: revision history revision section/figure/entry correction ds00002020a (10-09-15) replaces previous smsc version rev. 0.11 (03-03-05)
? 2005 - 2015 microchip technology inc. ds00002020a-page 105 SIO1007 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), te chnical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchip?s customer notification servic e helps keep customers current on microc hip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notifi- cation? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://www.microchip.com/support
SIO1007 ds00002020a-page 106 ? 2005 - 2015 microchip technology inc. product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . part no. (1) xxx (2) package device device: SIO1007 (1) package: jv = 64-pin stqfp (2) tape and reel option: blank = tray packaging tr = tape and reel (3) example: SIO1007-jv = 64-pin stqfp [x] (3) tape and reel option - note 1: these products meet the halogen maxi- mum concentration values per iec61249-2-21. 2: all package options are rohs compliant. for rohs compliance and environmental information, please visit http:// www.microchip.com/pagehandler/en-us/ aboutus/ehs.html . 3: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. -
? 2005 - 2015 microchip technology inc. ds00002020a-page 107 SIO1007 information contained in this publication r egarding device applications and the like is provided only for your convenience and may be super- seded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no rep- resentations or warranties of any kind whether ex press or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liability arising from this information and its use. use of micro- chip devices in life support and/or safety applications is entir ely at the buyer?s risk, and the buyer agrees to defend, indemn ify and hold harmless microchip from any and all damages, claims, suits, or ex penses resulting from such use. no licenses are conveyed, impl icitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, dspic, flashf lex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technolog y incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered tradem arks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kl eernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, pi cdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, va risense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incor porated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. silicon storage technology is a regi stered trademark of microchip tech nology inc. in other countries. gestic is a registered trademark of microchi p technology germany ii gmbh & co. kg, a s ubsidiary of microchip technology inc., i n other countries. all other trademarks mentioned herein are property of their respective companies. ? 2005 - 2015, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 9781632778765 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem by dnv == iso/ts 16949 ==
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